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STK14C88-3NF45I Fiches technique(PDF) 11 Page - Cypress Semiconductor |
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STK14C88-3NF45I Fiches technique(HTML) 11 Page - Cypress Semiconductor |
11 / 18 page STK14C88-3 Document Number: 001-50592 Rev. *D Page 11 of 18 Table 3. SRAM Write Cycle Parameter Description 35 ns 45 ns Unit Min Max Min Max Cypress Parameter Alt tWC tAVAV Write Cycle Time 35 45 ns tPWE tWLWH, tWLEH Write Pulse Width 25 30 ns tSCE tELWH, tELEH Chip Enable To End of Write 25 30 ns tSD tDVWH, tDVEH Data Setup to End of Write 12 15 ns tHD tWHDX, tEHDX Data Hold After End of Write 0 0 ns tAW tAVWH, tAVEH Address Setup to End of Write 25 30 ns tSA tAVWL, tAVEL Address Setup to Start of Write 0 0 ns tHA tWHAX, tEHAX Address Hold After End of Write 0 0 ns tHZWE [11,12] tWLQZ Write Enable to Output Disable 13 15 ns tLZWE [11] tWHQX Output Active After End of Write 5 5 ns Switching Waveforms Figure 9. SRAM Write Cycle 1: WE Controlled [13, 14] Figure 10. SRAM Write Cycle 2: CE Controlled [13, 14] tWC tSCE tHA tAW tSA tPWE tSD tHD tHZWE tLZWE ADDRESS CE WE DATA IN DATA OUT DATA VALID HIGH IMPEDANCE PREVIOUS DATA tWC ADDRESS tSA tSCE tHA tAW tPWE tSD tHD CE WE DATA IN DATA OUT HIGH IMPEDANCE DATA VALID Notes 12. If WE is Low when CE goes Low, the outputs remain in the high impedance state. 13. CE or WE must be greater than VIH during address transitions. 14. HSB must be HIGH during SRAM WRITE cycles. [+] Feedback [+] Feedback |
Numéro de pièce similaire - STK14C88-3NF45I |
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Description similaire - STK14C88-3NF45I |
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