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TPS53317 Fiches technique(PDF) 11 Page - Texas Instruments

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No de pièce TPS53317
Description  3.3-V/5-V Input, 6-A, D-CAP Mode Synchronous Step-Down Integrated FETs
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

TPS53317 Fiches technique(HTML) 11 Page - Texas Instruments

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=
´
OUT
ON
IN
SW
V
1
t
V
f
+
VREFIN
+
RC
PWM
Comparator
RDS(on)
GMV = 1 mS
Driver
LOUT
ESR
COUT
ROUT
UDG-11168
RLOAD
8 kW
+
+
GMC= 1 mS
CC
VREF
+
TPS53317
www.ti.com
SLUSAK4
– JUNE 2011
PWM Frequency and Adaptive on Time Control
In general, the on-time (at the SW node) can be estimated by Equation 1.
where
fSW is the frequency selected by the connection of the MODE pin
(1)
The on-time pulse is sent to the top FET. The inductor current and the current feedback rises to peak value.
Each ON pulse is latched to prevent double pulsing. Switching frequency settings are shown in .
Non-Droop Configuration
The TPS53317 can be configured as a non-droop solution. The benefit of a non-droop approach is that load
regulation is flat, therefore, in a system where tight DC tolerance is desired, the non-droop approach is
recommended. For the Intel system agent application, non-droop is recommended as the standard configuration.
The non-droop approach can be implemented by connecting a resistor and a capacitor between the COMP and
the VREF pins. The purpose of the type II compensation is to obtain high DC feedback gain while minimizing the
phase delay at unity gain cross over frequency of the converter.
The value of the resistor (RC) can be calculated using the desired unity gain bandwidth of the converter, and the
value of the capacitor (CC) can be calculated by knowing where the zero location is desired. An application tool
that calculates these values is available from your local TI Field Application Engineer.
Figure 4 shows the basic implementation of the non-droop mode using the TPS53317.
Figure 4. Non-Droop Mode Basic Implementation
Copyright
© 2011, Texas Instruments Incorporated
11


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