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ADV7511W Fiches technique(PDF) 4 Page - Analog Devices |
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ADV7511W Fiches technique(HTML) 4 Page - Analog Devices |
4 / 12 page ADV7511W Rev. 0 | Page 4 of 12 Parameter Test Conditions/ Comments Temp Test Level1 Min Typ Max Unit AUDIO AC TIMING SCLK Duty Cycle When N/2 Is an Even Number Full IV 40 50 60 % When N/2 Is an Odd Number Full IV 49 50 51 % I2S[3:0], SPDIF Setup Time (tASU) Full IV 2 ns I2S[3:0], SPDIF Hold Time (tAHLD) Full IV 2 ns LRCLK Setup Time (tASU) Full IV 2 ns LRCLK Hold Time (tAHLD) Full IV 2 ns CEC CEC_CLK Frequency Full VIII 3 124 100 MHz CEC_CLK Accuracy Full VIII −2 +2 % I2C INTERFACE SCL Clock Frequency Full 400 kHz SDA Setup Time (tDSU) Full 100 ns SDA Hold Time (tDHO) Full 100 ns Setup for Start (tSTASU) Full 0.6 μs Hold Time for Start (tSTAH) Full 0.6 μs Setup for Stop (tSTOSU) Full 0.6 μs 1 See the section. Explanation of Test Levels 2 This is measured at 0.9 V. The relationship between clock and data is programmable in 400 ps steps. 3 UI is the unit interval. 4 12 MHz crystal oscillator for default register settings. |
Numéro de pièce similaire - ADV7511W |
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Description similaire - ADV7511W |
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