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LS842_SOT-23 Fiches technique(PDF) 1 Page - Micross Components |
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LS842_SOT-23 Fiches technique(HTML) 1 Page - Micross Components |
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1 / 1 page Click To Buy Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems. FEATURES LOW DRIFT | V GS1‐2 / T| ≤40µV/°C LOW LEAKAGE IG = 10pA TYP. LOW NOISE en = 8nV/√Hz TYP. LOW OFFSET VOLTAGE | V GS1‐2|≤ 25mV ABSOLUTE MAXIMUM RATINGS @ 25°C (unless otherwise noted) Maximum Temperatures Storage Temperature ‐65°C to +150°C Operating Junction Temperature +150°C Maximum Voltage and Current for Each Transistor – Note 1 ‐VGSS Gate Voltage to Drain or Source 60V ‐VDSO Drain to Source Voltage 60V ‐IG(f) Gate Forward Current 50mA Maximum Power Dissipation Device Dissipation @ Free Air – Total 400mW @ +125°C MATCHING CHARACTERISTICS @ 25°C UNLESS OTHERWISE NOTED SYMBOL CHARACTERISTICS VALUE UNITS CONDITIONS | V GS1‐2 / T| max. DRIFT VS. TEMPERATURE 40 µV/°C VDG=20V, ID=200µA TA=‐55°C to +125°C | V GS1‐2 | max. OFFSET VOLTAGE 25 mV VDG=20V, ID=200µA ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted) SYMBOL CHARACTERISTICS MIN. TYP. MAX. UNITS CONDITIONS BVGSS Breakdown Voltage 60 60 ‐‐ V VDS = 0 ID=1nA BVGGO Gate‐To‐Gate Breakdown 60 ‐‐ ‐‐ V I G= 1nA ID= 0 IS= 0 YfSS TRANSCONDUCTANCE Full Conduction 1000 ‐‐ 4000 µmho VDG= 20V VGS= 0V f = 1kHz YfS Typical Operation 500 ‐‐ 1000 µmho VDG= 20V ID= 200µA |YFS1‐2 / Y FS| Mismatch ‐‐ 0.6 3 % IDSS DRAIN CURRENT Full Conduction 0.5 2 5 mA VDG= 20V VGS= 0V |IDSS1‐2 / IDSS| Mismatch at Full Conduction ‐‐ 1 5 % VGS(off) or Vp GATE VOLTAGE Pinchoff voltage 1 2 4.5 V VDS= 20V ID= 1nA VGS(on) Operating Range 0.5 ‐‐ 4 V VDS=20V ID=200µA ‐IGmax. GATE CURRENT Operating ‐‐ 10 50 pA VDG= 20V ID= 200µA ‐IGmax. High Temperature ‐‐ ‐‐ 50 nA TA= +125°C ‐IGmax. Reduced VDG ‐‐ 5 ‐‐ pA VDG = 10V ID= 200µA ‐IGSSmax. At Full Conduction ‐‐ ‐‐ 100 pA VDG= 20V , VDS =0 YOSS OUTPUT CONDUCTANCE Full Conduction ‐‐ ‐‐ 10 µmho VDG= 20V VGS= 0V YOS Operating ‐‐ 0.1 1 µmho VDG= 20V ID= 200µA |YOS1‐2| Differential ‐‐ 0.01 0.1 µmho CMR COMMON MODE REJECTION ‐20 log | V GS1‐2/ V DS| ‐‐ 100 ‐‐ dB ∆VDS = 10 to 20V ID=200µA ‐20 log | V GS1‐2/ V DS| ‐‐ 75 ‐‐ ∆VDS = 5 to 10V ID=200µA NF NOISE Figure ‐‐ ‐‐ 0.5 dB VDS= 20V VGS= 0V RG= 10MΩ f= 100Hz NBW= 6Hz en Voltage ‐‐ ‐‐ 10 nV/√Hz VDS=20V ID=200µA f=1KHz NBW=1Hz ‐‐ ‐‐ 15 VDS=20V ID=200µA f=10Hz NBW=1Hz CISS CAPACITANCE Input ‐‐ 4 10 pF VDS= 20V, ID=200µA CRSS Reverse Transfer ‐‐ 1.2 5 CDD Drain‐to‐Drain ‐‐ 0.1 ‐‐ LS842 MONOLITHIC DUAL N-CHANNEL JFET Linear Systems Ultra Low Leakage Low Drift Monolithic Dual JFET LS842 Applications: Wideband Differential Amps High-Speed,Temp-Compensated Single- Ended Input Amps High-Speed Comparators Impedance Converters and vibrations detectors. The LS842 is a high-performance monolithic dual JFET featuring extremely low noise, tight offset voltage and low drift over temperature specifications, and is targeted for use in a wide range of precision instrumentation applications. The LS842 features a 25- mV offset and 40-µV/°C drift. The 6 Pin SOT-23 package provides ease of manufacturing, and a lower cost assembly option. (See Packaging Information). Available Packages: LS842 / LS842 in SOT-23 LS842 / LS842 available as bare die Please contact Micross for full package and die dimensions Note 1 – These ratings are limiting values above which the serviceability of any semiconductor may be impaired Tel: +44 1603 788967 Email: chipcomponents@micross.com Web: http://www.micross.com/distribution |
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