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FAN3227C Fiches technique(PDF) 2 Page - Fairchild Semiconductor

No de pièce FAN3227C
Description  2A Low-Voltage PMOS-NMOS Bridge Driver
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Fabricant  FAIRCHILD [Fairchild Semiconductor]
Site Internet  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

FAN3227C Fiches technique(HTML) 2 Page - Fairchild Semiconductor

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© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN3268 • Rev. 1.0.1
2
Ordering Information
Part Number
Logic
Input Threshold
Packing Method
FAN3268TMX
Non-Inverting Channel and Inverting
Channel + Dual Enables
TTL
2,500 Units on
Tape & Reel
Package Outline
Figure 2. Pin Configuration (Top View)
Thermal Characteristics
(1)
Package
JL
(2)
JT
(3)
JA
(4)
JB
(5)
JT
(6)
Units
8-Pin Small Outline Integrated Circuit (SOIC)
40
31
89
43
3
°C/W
Notes:
1.
Estimates derived from thermal simulation; actual values depend on the application.
2.
Theta_JL (
JL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any
thermal pad) that are typically soldered to a PCB.
3.
Theta_JT (
JT): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is
held at a uniform temperature by a top-side heatsink.
4.
Theta_JA (ΘJA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow.
The value given is for natural convection with no heatsink using a 2S2P board, as specified in JEDEC standards JESD51-2,
JESD51-5, and JESD51-7, as appropriate.
5.
Psi_JB (
JB): Thermal characterization parameter providing correlation between semiconductor junction temperature and an
application circuit board reference point for the thermal environment defined in Note 4. For the SOIC-8 package, the board
reference is defined as the PCB copper adjacent to pin 6.
6.
Psi_JT (
JT): Thermal characterization parameter providing correlation between the semiconductor junction temperature and
the center of the top of the package for the thermal environment defined in Note 4.


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