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FQA13N50C Datasheet(Fiches technique) 5 Page - Fairchild Semiconductor

Numéro de pièce FQA13N50C
Description  PFCPWM Combination Controller
Télécharger  17 Pages
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Fabricant  FAIRCHILD [Fairchild Semiconductor]
Site Internet  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

FQA13N50C Datasheet(HTML) 5 Page - Fairchild Semiconductor

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AN-8027
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
Rev. 1.0.0 • 8/26/09
5
Design Considerations
In this section, a design procedure is presented using the
schematic in Figure 11 as reference. A 300W PC power
supply application with universal input range is selected as
a design example. The design specifications are
summarized in 0. The two-switch forward converter is used
for DC/DC converter stage.
Design Specifications
Rated Voltage of Output 1
VOUT1 = 5V
PWM Stage Efficiency
ηPWM = 0.86
Rated Current of Output 1
IOUT1 = 9A
Hold-up Time
tHLD = 20ms
Rated Voltage of Output 2
Vout2 = 12V
Minimum PFC Output Voltage
310V
Rated Current of Output 2
IOUT2 = 16.5A
Nominal PFC output voltage
VO_PFC = 387V
Rated Voltage of Output 3
VOUT3 = -12V
PFC Output Voltage Ripple
12VPP
Rated Current of Output 3
IOUT3 = 0.8A
PFC Inductor Ripple Current
dI = 40%
Rated Voltage of Output 4
VOUT4 = 3.3V
AC Input Voltage Frequency
fline = 50 ~ 60Hz
Rated Current of Output 4
IOUT4 = 13.5A
Switching Frequency
fS = 65KHz
Rated Output Power
PO = 300W
Total Harmonic Distortion
α = 4%
Line Voltage Range
85~264VAC
Magnetic Flux Density
ΔB = 0.27T
Line Frequency
50Hz
Current Density
Dcma = 400C-m/A
Brownout Protection Line Voltage
72VAC
PWM Maximum Duty Cycle
Dmax = 0.35
Overall Stage Efficiency
η = 0.82
5V Output Current Ripple
ILo1 = 44%
12V Output Current Ripple
ILo2 = 10%
D
BOOST
L BOOST
Q1
C
BOOST
R
CS1
C
IF1
F1
IEA
RAMP
RT/CT
FBPWM
SS
VRMS
ISENSE
IAC
ILIMIT
GND
OPWM
OPFC
VD
D
VREF
FBPFC
VEA
R
FB2
RFB1
Q2
Q3
D
R1
L 1
1
L 2
1
C
O11
L 1
2
L22
V
o1
V
o2
V D
D
AC
Input
RRAMP
FAN480X
Drv
R IAC
Drv
Drv
C
O12
C
O21
C
O22
D
F1
D
F2
D
R2
V
BOUT
C
FB
C
REF
C
DD
C
LF2
R
LF2
R
CS2
D
R1
D
R2
R
RMS2
C
RMS1
C
RMS2
C
LF1
C
SS
C
T
C
RAMP
R
T
R
IC
C
IC1
C
IC2
D1
D2
R
RMS1
R
RMS3
R
B
C
VC2
C
VC1
R
VC
C
B
V
o1
V
o2
R
D
R
BIAS
R
OS1
R
OS2
R
OS3
R
F
C
F
R
LF1
V
o3
V
o4
Figure 11. Reference Circuit for Design Example


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