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FAN6921 Fiches technique(PDF) 8 Page - Fairchild Semiconductor |
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FAN6921 Fiches technique(HTML) 8 Page - Fairchild Semiconductor |
8 / 16 page AN-6921 APPLICATION NOTE © 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com Rev. 1.0.1 • 8/24/10 8 Part B. DC/DC Section [STEP-B1] Determine the Reflected Output Voltage (VRO) Figure 11 shows the typical operation waveforms of a quasi- resonant flyback converter. When the MOSFET is turned off, the input voltage (PFC output voltage), together with the output voltage reflected to the primary (VRO), is imposed on the MOSFET. When the MOSFET is turned on, the sum of input voltage reflected to the secondary side and the output voltage is applied across the diode. Thus, the maximum nominal voltage across the MOSFET (Vds nom) and diode are given as: .. .. () nom DS O PFC H O F O PFC H RO VV n V V V V =+ + = + where: RO OF V n VV = + (20) .. .. () nom O PFC H O PFC H DO O O F RO VV VV V V V nV =+ =+ + (21) By increasing VRO (i.e. the turns ratio, n), the capacitive switching loss and conduction loss of the MOSFET are reduced. This also reduces the voltage stress of the secondary-side rectifier diode. However, this increases the voltage stress on the MOSFET. Therefore, VRO should be determined by a trade-off between the voltage stresses of the MOSFET and diode. It is typical to set VRO such that VDS norm and VD nom are 75~85% of their voltage ratings. Figure 11. Typical Waveforms of QR Flyback Converter (Design Example) Assuming 650V MOSFET and 100V MOSFET are used for primary side and secondary side, respectively, with 18% voltage margin: . . 0.82 650 0.82 650 133 nom DSO PFC RO RO O PFC VV V V VV V ⋅> = + ∴< ⋅ − = . . 0.82 100 ( ) ( ) 121 0.82 100 nom OPFC DO O F RO nom OPFC RO D O F O V VV V V V V VV V V V V ⋅> = + + ∴> = + = ⋅− VRO is determined as 130V. [STEP-B2] Transformer Design Figure 12 shows the typical switching timing of a quasi- resonant converter. The sum of MOSFET conduction time (tON), diode conduction time (tD), and drain voltage falling time (tF) is the switching period (tS). To determine the primary-side inductance (Lm), the following parameters should be determined first. Minimum Switching Frequency ( fS.QR min) The minimum switching frequency occurs at the minimum input voltage and full-load condition, which should be higher than 20kHz to avoid audible noise. By increasing fS.QR min, the transformer size can be reduced. However, this results in increased switching losses. Determine fS.QR min by a trade-off between switching losses and transformer size. Typically fS.QR min is set to around 50kHz. Falling Time of the MOSFET Drain Voltage (tF) As shown in Figure 12, the MOSFET drain voltage fall time is half of the resonant period of the MOSFET’s effective output capacitance and primary-side inductance. The typical value for tF is 0.6~1.2µs. Non-Conduction Time of the MOSFET (tOFF) FAN6921 has a minimum non-conduction time of MOSFET (8µs), during which turning on of MOSFET is prohibited. To maximize the efficiency, it is necessary to turn on the MOSFET at the first valley of MOSFET drain-to-source voltage at heavy-load condition. Therefore, the MOSFET non-conduction time at heavy load condition should be larger than 8µs. After determining fS.QR min and tF, the maximum duty cycle is calculated as: min max . .. (1 ) RO SQR F RO O PFC L V D ft VV = ⋅− ⋅ + (22) Then, the primary-side inductance is obtained as: 2 .. max min . () 2 QR O PFC L m SQR OUT VD L fP η ⋅⋅ = ⋅ (23) |
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