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CD-700 Fiches technique(PDF) 2 Page - Vectron International, Inc

No de pièce CD-700
Description  Complete VCXO Based Phase Lock Loop
Download  12 Pages
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Fabricant  VECTRON [Vectron International, Inc]
Site Internet  http://www.vectron.com
Logo VECTRON - Vectron International, Inc

CD-700 Fiches technique(HTML) 2 Page - Vectron International, Inc

  CD-700_09 Datasheet HTML 1Page - Vectron International, Inc CD-700_09 Datasheet HTML 2Page - Vectron International, Inc CD-700_09 Datasheet HTML 3Page - Vectron International, Inc CD-700_09 Datasheet HTML 4Page - Vectron International, Inc CD-700_09 Datasheet HTML 5Page - Vectron International, Inc CD-700_09 Datasheet HTML 6Page - Vectron International, Inc CD-700_09 Datasheet HTML 7Page - Vectron International, Inc CD-700_09 Datasheet HTML 8Page - Vectron International, Inc CD-700_09 Datasheet HTML 9Page - Vectron International, Inc Next Button
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Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Page 2 of 12
1. A 0.01uF and 0.1uF parallel capacitor should be located as close to pin 14 as possible (and grounded).
2. Figure 2 defines these parameters. Figure 3 illustrates the equivalent five gate TTL load and operating conditions under which these parameters
are tested and specified. Loads greater than 15 pF will adversely effect rise/fall time as well as symmetry.
3. Symmetry is defined as (ON TIME/PERIOD with Vs=1.4 V for both 5.0 V and 3.3 V operation.
Figure 2. Output Waveform
Figure 3. OUT1, OUT2, RCLK, RDATA Test Conditions (25 ±50C)
Performance Specifications
Table 1. Electrical Performance
Parameter
Symbol
Min
Typical
Maximum
Units
Output Frequency
(ordering option)
OUT 1, 5.0 V option
OUT 1, 3.3 V option
1.000
1.000
77.760
77.760
MHz
MHz
Supply Voltage1
+5.0
+3.3
V
DD
4.5
2.97
5.0
3.3
5.5
3.63
V
V
Supply Current
I
DD
63
mA
Output Logic Levels
Output Logic High2
Output Logic Low2
V
OH
V
OL
2.5
0.5
V
V
Output Transition Times
Rise Time2
Fall Time2
t
R
t
F
3.0
3.0
ns
ns
Input Logic Levels
Input Logic High2
Input Logic Low2
V
IH
V
IL
2.0
0.5
V
V
Loss of Signal Indication
Output Logic High2
Output Logic Low2
V
OH
V
OL
2.5
0.5
V
V
Nominal Frequency on Loss of Signal
Output 1
Output 2
±75
±75
ppm
ppm
Symmetry or Duty Cycle3
Out 1
Out 2
RCLK
SYM1
SYM2
RCLK
40/60
45/55
40/60
%
%
%
Absolute Pull Range
(ordering option)
over operating temperure, aging, and power
supply variations
APR
±50
±80
±100
ppm
Test Conditions for APR (+5.0 V option)
V
C
0.5
4.5
V
Test Conditions for APR (+3.3 V option)
V
C
0.3
3.0
V
Gain Transfer
Kv
Positive
Phase Detector Gain
+5.0 V option
+3.3 V option
Kv
0.53
0.35
rad/V
rad/V
Operating temperature
(ordering option)
T
OP
0/70 or -40/85
°C
Control Voltage Leakage Current
I
VCXO
±1.0
μA
Rev: 30Mar2009


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