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CD-700 Fiches technique(PDF) 5 Page - Vectron International, Inc
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VECTRON [Vectron International, Inc]
CD-700 Fiches technique(HTML) 5 Page - Vectron International, Inc
/ 12 page
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Page 5 of 12
Loss of Signal, LOS and LOSIN
The LOS circuit provides an output alarm flag when the DATAIN input signal is lost. The LOS output is normally a logic low
and is set to a logic high after 256 consecutive clock periods on CLKIN with no detected DATAIN transitions. This signal can be
used to either flag external alarm circuits and/or drive the CD-700’s LOSIN input. When LOSIN is set to a logic high, the VCXO
control voltage (pin 16) is switched to an internal voltage which sets OUT1 and OUT2 to center frequency +/-75ppm. Also, LOS
automatically closes the op amp feedback which means the op-amp is a unity gain buffer and will produce a DC voltage equal to
the +op amp voltage (pin 15), usually VDD/2.
VCXO and Absolute Pull Range (APR) Specification
The CD-700’s VCXO is a varactor tuned crystal oscillator, which produces an output frequency proportional to the control voltage
(pin 16). The frequency deviation of the CD-700 VCXO is specified in terms of Absolute Pull Range (APR). APR provides the user
with a guaranteed specification for minimum available frequency deviation over all operating conditions. Operating conditions
include power supply variation, operating temperature range, and differences in output loading and changes due to aging.
A CD-700 VCXO with an APR of +/-50 ppm will track a +/-50 ppm reference source over all operating conditions. The fourth
character of the product code in Table 7 specifies absolute Pull Range (APR). Please see Vectron’s web site (www.vectron.com) for
the APR Application Note. APR is tested at 0.5 and 4.5 volts for the 5.0 volt option and 0.3 and 3.0 volts for the 3.3 volt option.
Quartz oscillators typically exhibit a part per million shift in output frequency during aging. The major factors, which lead to this
shift, are changes in the mechanical stress on the crystal and mass-loading on the crystal.
As the oscillator ages, relaxation of the crystal mounting stress or transfer of environmental stress through the package to the
crystal mounting arrangement can lead to frequency variations. VI has minimized these two effects through the use of a miniature
AT-cut strip resonator crystal which allows a superior mounting arrangement. This results in minimal relaxation and almost
negligible environmental stress transfer.
VI has eliminated the impact of mass loading by ensuring hermetic integrity and minimizing out-gassing by limiting the number
of internal components through the use of ASIC technology. Mass-loading on the crystal generally results in a frequency decrease
and is typically due to out-gassing of material within a hermetic package or from contamination by external material in a non-
hermetic package. Under normal operating conditions the CD-700 will typically exhibit 2 ppm aging in the first year of operation.
The device will then typically exhibit 1 ppm aging the following year with a logarithmic decline each year thereafter.
Frequency Divider Feature
The lowest available VCXO OUT1 frequency is 1.000 MHz. To achieve lower frequencies, OUT1 is divided by a 2n counter (n = 1 to
8) and is the OUT2 frequency. The divider values (2, 4, 8, 16, 32, 64, 128 and 256) are set at the factory, so it is user selectable upon
ordering only. In addition, a disabled OUT2 option is also available. To achieve 1.024 MHz, a CD-700 with OUT1 frequency equal
to 16.384 MHz and a divider value equal to 16 would be used. Additional external divider circuits can be used to further lower or
change the frequency.
A PLL is a feedback system which forces the output frequency to lock in both phase and frequency to the input frequency. While
there will be some phase error, theory states there is no frequency error. The loop filter design will dictate many key parameters
such as jitter reduction, stability, lock range and acquisition time. Be advised that many textbook equations describing loop
dynamics, such as capture range are based on ideal systems. Such equations may not be accurate for real systems due to
nonlinearities, DC offsets, noise and do not take into account the limited VCXO bandwidth. This section deals with some real world
design examples. Also, there is loop filter software on the Vectron web site, plus a full staff of experienced applications engineers
who are eager to assist in this process. Common CD-700 PLL applications are shown in Figures 8, 9 (frequency translation), Figure
10 (clock recovery) and Figure 11 (clock smoothing).
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