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ISL29027 Fiches technique(PDF) 4 Page - Intersil Corporation

No de pièce ISL29027
Description  Proximity Sensor with Intelligent Interrupt and Sleep Modes
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Fabricant  INTERSIL [Intersil Corporation]
Site Internet  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL29027 Fiches technique(HTML) 4 Page - Intersil Corporation

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ISL29027
4
FN7815.0
February 7, 2011
PSRRIRDR
(
ΔIIRDR)/(ΔVIRDR)
PROX_DR = 0; VIRDR = 0.5V to 4.3V
4
mA/V
NOTES:
7. An 850nm infrared LED is used to test PROX/IR sensitivity in an internal test mode.
8. Ability to guarantee IIRDR leakage of ~1nA is limited by test hardware..
9. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
Electrical Specifications VDD = 3.0V, TA = +25°C, REXT = 499kΩ 1% tolerance. (Continued)
PARAMETER
DESCRIPTION
CONDITION
MIN
(Note 9) TYP
MAX
(Note 9) UNIT
I2C Electrical Specifications For SCL and SDA unless otherwise noted, VDD = 3V, TA = +25°C, REXT = 499kΩ 1% tolerance
(Note 10).
PARAMETER
DESCRIPTION
CONDITION
MIN
TYP MAX
UNIT
VI2C
Supply Voltage Range for I2C Interface
1.7
3.63
V
fSCL
SCL Clock Frequency
400
kHz
VIL
SCL and SDA Input Low Voltage
0.55
V
VIH
SCL and SDA Input High Voltage
1.25
V
Vhys
Hysteresis of Schmitt Trigger Input
0.05VDD
V
VOL
Low-level Output Voltage (Open-drain) at 4mA Sink
Current
0.4
V
Ii
Input Leakage for each SDA, SCL Pin
-10
10
µA
tSP
Pulse Width of Spikes that must be Suppressed by
the Input Filter
50
ns
tAA
SCL Falling Edge to SDA Output Data Valid
900
ns
Ci
Capacitance for each SDA and SCL Pin
10
pF
tHD:STA
Hold Time (Repeated) START Condition
After this period, the first clock pulse is
generated
600
ns
tLOW
LOW Period of the SCL Clock
Measured at the 30% of VDD crossing
1300
ns
tHIGH
HIGH period of the SCL Clock
600
ns
tSU:STA
Set-up Time for a Repeated START Condition
600
ns
tHD:DAT
Data Hold Time
30
ns
tSU:DAT
Data Set-up Time
100
ns
tR
Rise Time of both SDA and SCL Signals
(Note 11)
20 + 0.1xCb
ns
tF
Fall Time of both SDA and SCL Signals
(Note 11)
20 + 0.1xCb
ns
tSU:STO
Set-up Time for STOP Condition
600
ns
tBUF
Bus Free Time Between a STOP and START
Condition
1300
ns
Cb
Capacitive Load for Each Bus Line
400
pF
Rpull-up
SDA and SCL System Bus Pull-up Resistor
Maximum is determined by tR and tF
1k
Ω
tVD;DAT
Data Valid Time
0.9
µs
tVD:ACK
Data Valid Acknowledge Time
0.9
µs
VnL
Noise Margin at the LOW Level
0.1VDD
V
VnH
Noise Margin at the HIGH Level
0.2VDD
V
NOTES:
10. All parameters in I2C Electrical Specifications table are guaranteed by design and simulation.
11. Cb is the capacitance of the bus in pF.


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