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LC651104L Fiches technique(PDF) 9 Page - Sanyo Semicon Device

No de pièce LC651104L
Description  On-Chip UVEPROM 4-Bit Single-Chip Microcontroller
Download  19 Pages
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Fabricant  SANYO [Sanyo Semicon Device]
Site Internet  https://www.sanyo-av.com/us/
Logo SANYO - Sanyo Semicon Device

LC651104L Fiches technique(HTML) 9 Page - Sanyo Semicon Device

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No. 5221-9/19
LC65E1104
Parameter
Symbol
Conditions
Ratings
Unit
Maximum supply voltage
VDD max
VDD
–0.3 to +7.0
V
Output voltage
VO
OSC2
Allowable up to the
V
generated voltage
Input voltage
VI1
OSC1*1
–0.3 to VDD + 0.3
V
VI2
TEST, RES, AV+, AV–
–0.3 to VDD + 0.3
V
Input/output voltage
VIO1
PC0 to PC3, PD0 to PD3, PE0, PE1, PF0 to PF3
–0.3 to +15
V
VIO2
PA0 to PA3, PG0 to PG3
–0.3 to VDD + 0.3
V
Peak output current
IOP
I/O port
–2 to +20
mA
IOA
I/O port: Per pin over a 100 ms period
–2 to +20
mA
ΣIOA1
PC0 to PC3, PD0 to PD3, PE0, PE1:Total current for
–15 to +100
mA
Average output current
PC0 to PC3, PD0 to PD3, and PE0, PE1*2
ΣIOA2
PF0 to PF3, PG0 to PG3, PA0 to PA3: Total current for
–15 to +100
mA
PF0 to PF3, PG0 to PG3, and PA0 to PA3*2
Allowable power dissipation
Pd max1
Ta = +10 to +40°C (DIC package)
250
mW
Pd max2
Ta = +10 to +40°C (MFC package)
150
mW
Operating temperature
Topr
+10 to +40
°C
Storage temperature
Tstg
–55 to +125
°C
Specifications
For LC651104N, 651102N
Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Operating supply voltage
VDD
VDD
3.0
6.0
V
Standby supply voltage
VST
VDD: RAM, register hold*3
1.8
6.0
V
VIH1
Port C, D, E, F: Output Nch Tr. off
0.7 VDD
+13.5
V
VIH2
Port A, G: Output Nch Tr. off
0.7 VDD
VDD
V
High level input voltage
VIH3
INT, SCK, SI: Output Nch Tr. off
0.8 VDD
+13.5
V
VIH4
RES: VDD = 1.8 to 6 V
0.8 VDD
VDD
V
VIH5
OSC1: External clock mode
0.8 VDD
VDD
V
VIL1
Port: Output Nch Tr. off, VDD = 4 to 6 V
VSS
0.3 VDD
V
VIL2
Port: Output Nch Tr. off, VDD = 3 to 6 V
VSS
0.25 VDD
V
VIL3
INT, SCK, SI: Output Nch Tr. off, VDD = 4 to 6 V
VSS
0.25 VDD
V
VIL4
INT, SCK, SI: Output Nch Tr. off, VDD = 3 to 6 V
VSS
0.2 VDD
V
Low level input voltage
VIL5
OSC1: External clock mode, VDD = 4 to 6 V
VSS
0.25 VDD
V
VIL6
OSC1: External clock mode, VDD = 3 to 6 V
VSS
0.2 VDD
V
VIL7
TEST: VDD = 4 to 6 V
VSS
0.3 VDD
V
VIL8
TEST: VDD = 3 to 6 V
VSS
0.25 VDD
V
VIL9
RES: VDD = 4 to 6 V
VSS
0.25 VDD
V
VIL10
RES: VDD = 3 to 6 V
VSS
0.2 VDD
V
Operating frequency
fop
When the 1/3 or 1/4 predivider option is selected,
200
1444
kHz
(cycle time)
(Tcyc)
clock must not exceed 4.33 MHz. VDD = 3 to 6 V
(20)
(2.77)
(µs)
[External clock conditions]
Frequency
text
OSC1: Fig 1, when clock exceeds 1.444 MHz,
200
4330
kHz
Pulse width
textH, textL
the 1/3 or 1/4 predivider option must be selected.
69
ns
Rise/fall time
textR, textF
VDD = 3 to 6 V
50
ns
[Oscillator guaranteed constants]
Cext
OSC1, OSC2: Fig 2, VDD = 3 to 6 V
270 ± 5%
pF
2-pin RC oscillator
Cext
OSC1, OSC2: Fig 2, VDD = 4 to 6 V
270 ± 5%
pF
Rext
OSC1, OSC2: Fig 2, VDD = 3 to 6 V
12 ± 1%
k
Rext
OSC1, OSC2: Fig 2, VDD = 4 to 6 V
4.7 ± 1%
k
Ceramic
Fig 3
Table 1
Allowable Operating Conditions at Ta = +10 to +40°C, VSS = 0 V, VDD = 3.0 to 6.0 V


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