LC651204F datasheet(11/35 Pages) SANYO

No de pièce	LC651204F

Description	4-Bit Single-Chip Microcontrollers for Small-Scale Control Applications

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Fabricant	SANYO [Sanyo Semicon Device]

Site Internet	https://www.sanyo-av.com/us/

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11 / 35 page

LC651204N, 651202N

Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V

No. 5190-11/35

LC651204N/F/L, LC651202N/F/L

Parameter

Symbol

Conditions

Applicable pins/notes

Ratings

Unit

Maximum supply voltage VDD max

VDD

–0.3 to +7.0

V

Voltages up to any

Output voltage

VO

OSC2

generated voltage are

V

allowed.

Input voltage

VI (1)

OSC1 *1

–0.3 to VDD +0.3

V

VI (2)

TEST, RES

–0.3 to VDD +0.3

V

VIO (1)

PC0 to 3, PD0 to 3, PE0, 1, PF0 to 3

OD specification ports

–0.3 to + 15

V

I/O voltage

VIO (2)

PC0 to 3, PD0 to 3, PE0, 1, PF0 to 3

PU specification ports

–0.3 to VDD +0.3

V

VIO (3)

PA0 to 3, PG0 to 3

–0.3 to VDD +0.3

V

Peak output current

IOP

I/O ports

–2 to +20

mA

IOA

Average value per pin over a 100-ms period

I/O ports

–2 to +20

mA

Σ I

OA

(1)

Total current for pins PC0 to 3, PD0 to 3, and

PC0 to PC3

PE0 to 1*2

PD0 to PD3

–15 to +100

mA

Average output current

PE0 to PE1

Σ I

OA

(2)

Total current for pins PF0 to 3, PG0 to 3, and

PF0 to PF3

PA0 to 3*2

PG0 to PG3

–15 to +100

mA

PA0 to PA3

Allowable power

Pd max (1) Ta = –40 to +85°C (DIP package)

250

mW

dissipation

Pd max (2) Ta = –40 to +85°C (MFP package)

150

mW

Operating temperature

Topr

–40 to +85

°C

Storage temperature

Tstg

–55 to +125

°C

Allowable Operating Ranges at Ta = –40 to 85°C, VSS = 0 V, VDD = 3.0 to 5.5 V (unless otherwise specified)

Parameter

Symbol

Conditions

Applicable pins/notes

Ratings

min

typ

max

Unit

Operating power-supply

V

DD

V

DD

3.0

5.5

V

voltage

Standby power-supply

V

ST

RAM and register values retained *3

V

DD

1.8

5.5

V

voltage

V

IH (1)

Output n-channel transistors off

OD specification ports C, D, E,

0.7 V

DD

13.5

V

and F

V

IH (2)

Output n-channel transistors off

PU specification ports C, D, E,

0.7 V

DD

V

DD

V

and F

VIH (3)

Output n-channel transistors off

Port A, G

0.7 VDD

VDD

V

Input high-level voltage

V

IH (4)

Output n-channel transistors off

The INT, SCK, and SI pins with

0.8 V

DD

13.5

V

OD specifications

V

IH (5)

Output n-channel transistors off

The INT, SCK, and SI pins with

0.8 V

DD

V

DD

V

PU specifications

VIH (6)

VDD = 1.8 to 5.5 V

RES

0.8 VDD

VDD

V

VIH (7)

External clock specifications

OSC1

0.8 VDD

VDD

V

Continued on next page.

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