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74AHC259D Fiches technique(PDF) 10 Page - NXP Semiconductors |
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74AHC259D Fiches technique(HTML) 10 Page - NXP Semiconductors |
10 / 17 page 74AHC_AHCT259_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 15 May 2008 10 of 17 NXP Semiconductors 74AHC259; 74AHCT259 8-bit addressable latch Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. Address input to output propagation delays 001aah122 An input Qn output tPHL tPLH GND VCC VM VM VOH VOL Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Enable input to output propagation delays and pulse width 001aah121 LE input Qn output tPHL tPLH tW VM VOH VCC GND VCC GND VOL VM D input Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig 8. Conditional reset input to output propagation delays 001aah124 MR input Qn output tPHL tW VM VOH VCC GND VOL VM |
Numéro de pièce similaire - 74AHC259D |
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