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ADC11DS105CISQ Fiches technique(PDF) 4 Page - National Semiconductor (TI) |
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ADC11DS105CISQ Fiches technique(HTML) 4 Page - National Semiconductor (TI) |
4 / 24 page Pin No. Symbol Equivalent Circuit Description 57 20 PD_A PD_B This is a two-state input controlling Power Down. PD = V A, Power Down is enabled and power dissipation is reduced. PD = AGND, Normal operation. Note: This signal has no effect when SPI_EN is high and the SPI interface is enabled. 27 TEST Test Mode. When this signal is asserted high, a fixed test pattern (101001100011 msb->lsb) is sourced at the data outputs. With this signal deasserted low, the device is in normal operation mode. Note: This signal has no effect when SPI_EN is high and the SPI interface is enabled. 47 WAM Word Alignment Mode. In single-lane mode this pin must be set to logic-0. In dual-lane mode only, when this signal is at logic-0 the serial data words are offset by half-word. With this signal at logic-1 the serial data words are aligned with each other. Note: This signal has no effect when SPI_EN is high and the SPI interface is enabled. 48 DLC Dual-Lane Configuration. The dual-lane mode is selected when this signal is at logic-0. With this signal at logic-1, all data is sourced on a single lane (SD1_x) for each channel. Note: This signal has no effect when SPI_EN is high and the SPI interface is enabled. 45 44 OUTCLK+ OUTCLK- Serial Clock. This pair of differential LVDS signals provides the serial clock that is synchronous with the Serial Data outputs. A bit of serial data is provided on each of the active serial data outputs with each falling and rising edge of this clock. This differential output is always enabled while the device is powered up. In power- down mode this output is held in logic-low state. A 100-ohm termination resistor must always be used between this pair of signals at the far end of the transmission line. 43 42 FRAME+ FRAME- Serial Data Frame. This pair of differential LVDS signals transitions at the serial data word boundaries. The SD1_A+/- and SD1_B+/- output words always begin with the rising edge of the Frame signal. The falling edge of the Frame signal defines the start of the serial data word presented on the SD0_A+/- and SD0_B+/- signal pairs in the Dual-Lane mode. This differential output is always enabled while the device is powered up. In power-down mode this output is held in logic-low state. A 100-ohm termination resistor must always be used between this pair of signals at the far end of the transmission line. www.national.com 4 |
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