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ADC11DS105CISQ Fiches technique(PDF) 3 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
No de pièce ADC11DS105CISQ
Description  Dual 11-Bit, 105 MSPS A/D Converter with Serial LVDS Outputs
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Fabricant  NSC [National Semiconductor (TI)]
Site Internet  http://www.national.com
Logo NSC - National Semiconductor (TI)

ADC11DS105CISQ Fiches technique(HTML) 3 Page - National Semiconductor (TI)

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Pin Descriptions and Equivalent Circuits
Pin No.
Symbol
Equivalent Circuit
Description
ANALOG I/O
3
13
V
INA+
V
INB+
Differential analog input pins. The differential full-scale input signal
level is 2V
P-P with each input pin signal centered on a common
mode voltage, V
CM.
2
14
V
INA-
V
INB-
5
11
V
RPA
V
RPB
These pins should each be bypassed to AGND with a low ESL
(equivalent series inductance) 0.1 µF capacitor placed very close
to the pin to minimize stray inductance. An 0201 size 0.1 µF
capacitor should be placed between V
RP and VRN as close to the
pins as possible, and a 1 µF capacitor should be placed in parallel.
V
RP and VRN should not be loaded. VCMO may be loaded to 1mA
for use as a temperature stable 1.5V reference.
It is recommended to use V
CMO to provide the common mode
voltage, V
CM, for the differential analog inputs.
7
9
V
CMOA
V
CMOB
6
10
V
RNA
V
RNB
59
V
REF
Reference Voltage. This device provides an internally developed
1.2V reference. When using the internal reference, V
REF should be
decoupled to AGND with a 0.1 µF and a 1µF, low equivalent series
inductance (ESL) capacitor.
This pin may be driven with an external 1.2V reference voltage.
This pin should not be used to source or sink current.
29
LVDS_Bias
LVDS Driver Bias Resistor is applied from this pin to Analog
Ground. The nominal value is 3.6K
Ω
DIGITAL I/O
18
CLK
The clock input pin.
The analog inputs are sampled on the rising edge of the clock input.
28
Reset_DLL
Reset_DLL input. This pin is normally low. If the input clock
frequency is changed abruptly, the internal timing circuits may
become unlocked. Cycle this pin high for 1 microsecond to re-lock
the DLL. The DLL will lock in several microseconds after
Reset_DLL is asserted.
19
OF/DCS
This is a four-state pin controlling the input clock mode and output
data format.
OF/DCS = V
A, output data format is 2's complement without duty
cycle stabilization applied to the input clock
OF/DCS = AGND, output data format is offset binary, without duty
cycle stabilization applied to the input clock.
OF/DCS = (2/3)*V
A, output data is 2's complement with duty cycle
stabilization applied to the input clock
OF/DCS = (1/3)*V
A, output data is offset binary with duty cycle
stabilization applied to the input clock.
Note: This signal has no effect when SPI_EN is high and the SPI
interface is enabled.
3
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