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ISL5314INZ Fiches technique(PDF) 6 Page - Intersil Corporation |
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ISL5314INZ Fiches technique(HTML) 6 Page - Intersil Corporation |
6 / 17 page 6 FN4901.3 January 19, 2010 Analog Output IOUTA and IOUTB are complementary current outputs. They are generated by a 14-bit DAC that is capable of running at the full 125MSPS rate. The DDS clock also clocks the DAC. The sum of the two output currents is always equal to the full scale output current minus one LSB. If single-ended use is desired, a load resistor can be used to convert the output current to a voltage. It is recommended that the unused output be equally terminated. The voltage developed at the output must not violate the output voltage compliance range of -1.0V to +1.25V. RLOAD (the impedance loading each current output) should be chosen so that the desired output voltage is produced in conjunction with the output full scale current. If a known line impedance is to be driven, then the output load resistor should be chosen to match this impedance. The output voltage is shown in Equation 5: These outputs can be used in a differential-to-single-ended arrangement. This is typically done to achieve better harmonic rejection. Because of a mismatch in IOUTA and IOUTB, the transformer does not improve the harmonic rejection. However, it can provide voltage gain without adding distortion. The SFDR measurements in this data sheet were performed with a 1:1 transformer on the output of the DDS (see Figure 1). With the center tap grounded, the output swing of pins 17 and 18 will be biased at 0V. The loading as shown in Figure 1 will result in a 500mVP-P signal at the output of the transformer if the full scale output current of the DAC is set to 20mA. VOUT = 2 x IOUT x REQ, where REQ is 12.5Ω. Allowing the center tap to float will result in identical transformer output, however, the output pins of the DAC will have positive DC offset, which could limit the voltage swing available due to the output voltage compliance range. The 50 Ω load on the output of the transformer represents the load at the end of a ‘transmission line’, typically a spectrum analyzer, oscilloscope, or the next function in the signal chain. The necessity to have a 50 Ω impedance looking back into the transformer is negated if the DDS is only driving a short trace. The output voltage compliance range does limit the impedance that is loading the DDS output. Application Considerations Ground Plane Separate digital and analog ground planes should be used. All of the digital functions of the device and their corresponding components should be located over the digital ground plane and terminated to the digital ground plane. The same is true for the analog components and the analog ground plane. Pins 11 through 24 are analog pins, while all the others are digital. Noise Reduction To minimize power supply noise, 0.1 μF capacitors should be placed as close as possible to the power supply pins, AVDD and DVDD. Also, the layout should be designed using separate digital and analog ground planes and these capacitors should be terminated to the digital ground for DVDD and to the analog ground for AVDD. Additional filtering of the power supplies on the board is recommended. Power Supplies The DDS will provide the best SFDR (spurious free dynamic range) when using +5V analog and +5V digital power supply. The analog supply must always be +5V (±10%). The digital supply can be either a +3.3V (±10%), a +5V (±10%) supply, or anything in between. The DDS is rated to 125MSPS when using a +5V digital supply and 100MSPS when using a +3.3V digital supply. Improving SFDR +5V power supplies provides the best SFDR. Under some clock and output frequency combinations, particularly when the fCLK/fOUT ratio is less than 4, the user can improve SFDR even further by connecting the COMP2 pin (19) of the DDS to the analog power supply. The digital supply must be +5V if this option is explored. Improvements as much as 6dBc in the SFDR-to-Nyquist measurement were seen in the lab. FSK Modulation Binary frequency shift keying (BFSK) can be done by using the offset frequency register and the ENOFR pin. M-ary FSK or GFSK (Gaussian) can be done by continuously loading in new frequency words. The maximum FSK data rate of the ISL5314 depends on the way the user programs the device to do FSK, and the form of FSK. For example, simple BFSK is efficiently performed with the ISL5314 by loading the center frequency register with one frequency, the offset frequency register with another frequency, and toggling the ENOFR (enable offset frequency register) pin. The latency is fourteen CLK cycles between assertion of the ENOFR pin and the change occurring at the analog output. However, the change in frequency can be pipelined such that the ENOFR can be toggled at a rate up to as shown in Equation 6: (EQ. 4) IOUT(Full Scale) = (VFSADJ/RSET) x 32 (EQ. 5) VOUT = IOUT X RLOAD PIN 17 PIN 18 100 Ω ISL5314 50 Ω 50 Ω 50 Ω FIGURE 1. TRANSFORMER OUTPUT CIRCUIT OPTION IOUTB IOUTA VOUT = (2 x IOUT x REQ)VP-P REQ IS THE IMPEDANCE SPECTRUM ANALYZER 50 Ω REPRESENTS THE LOADING EACH OUTPUT (EQ. 6) ENOFRMAX = fCLK/2 ISL5314 |
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