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ISL54302 Fiches technique(PDF) 9 Page - Intersil Corporation |
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ISL54302 Fiches technique(HTML) 9 Page - Intersil Corporation |
9 / 16 page 9 March 19, 2008 Logic-Level Thresholds VLOGIC and GND power the internal logic level shifter stages, so VPLUS and VSS have no affect on logic thresholds. Thus, SX-CTRL, CS-LATCH receive thresholds which will remain constant, despite changes to VPLUS and VSS. Leakage Considerations Reverse ESD protection diodes are internally connected between each analog-signal pin and both VPLUS and VSS. One of these diodes conducts if any analog signal exceeds VPLUS or VSS. ISL54302 Device Programming Programming the device entails accessing the internal switch control registers. To write data into the register, the data must be transferred via the CS-LATCH pin. Via the CS-LATCH pin, the programmer has complete control as to “when” data is transferred to the internal latches. Until such time as the CS-LATCH pin is “toggled,” the device will remain as previously programmed. Therefore, data transitions on the SX-CTRL inputs will not effect the switch’s operational condition. ISL54302 |
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Description similaire - ISL54302 |
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