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KM44S32030 Fiches technique(PDF) 6 Page - Samsung semiconductor

No de pièce KM44S32030
Description  8M x 4Bit x 4 Banks Synchronous DRAM
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Fabricant  SAMSUNG [Samsung semiconductor]
Site Internet  http://www.samsung.com/Products/Semiconductor
Logo SAMSUNG - Samsung semiconductor

KM44S32030 Fiches technique(HTML) 6 Page - Samsung semiconductor

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KM44S32030
CMOS SDRAM
REV. 2 Mar. '98
Preliminary
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
Symbol
-8
-H
-L
-10
Unit
Note
Min
Max
Min
Max
Min
Max
Min
Max
CLK cycle time
CAS latency=3
tCC
8
1000
10
1000
10
1000
10
1000
ns
1
CAS latency=2
12
10
12
13
CLK to valid
output delay
CAS latency=3
tSAC
6
6
6
7
ns
1, 2
CAS latency=2
6
6
7
7
Output data
hold time
CAS latency=3
tOH
3
3
3
3
ns
2
CAS latency=2
3
3
3
3
CLK high pulse width
tCH
3
3
3
3.5
ns
3
CLK low pulse width
tCL
3
3
3
3.5
ns
3
Input setup time
tSS
2
2
2
2.5
ns
3
Input hold time
tSH
1
1
1
1.5
ns
3
CLK to output in Low-Z
tSLZ
1
1
1
1
ns
2
CLK to output
in Hi-Z
CAS latency=3
tSHZ
6
6
6
7
ns
CAS latency=2
6
6
7
7
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Note :


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