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KM4132G271BTQR-8 Fiches technique(PDF) 9 Page - Samsung semiconductor

No de pièce KM4132G271BTQR-8
Description  128K x 32bit x 2 Banks Synchronous Graphic RAM LVTTL
Download  51 Pages
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Fabricant  SAMSUNG [Samsung semiconductor]
Site Internet  http://www.samsung.com/Products/Semiconductor
Logo SAMSUNG - Samsung semiconductor

KM4132G271BTQR-8 Fiches technique(HTML) 9 Page - Samsung semiconductor

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KM4132G271B
CMOS SGRAM
- 9 -
Rev. 2.4 (May 1998)
OPERATING AC PARAMETER
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. This parameter means minimum CAS to CAS delay at block write cycle only.
4. In case of row precharge interrupt, auto precharge and read burst stop.
Note :
(AC operating conditions unless otherwise noted)
Parameter
Symbol
Version
Unit
Note
-7
-8
-10
Row active to row active delay
tRRD(min)
14
16
20
ns
1
RAS to CAS delay
tRCD(min)
16
16
20
ns
1
Row precharge time
tRP(min)
21
20
20
ns
1
Row active time
tRAS(min)
49
48
50
ns
1
tRAS(max)
100
us
Row cycle time
tRC(min)
70
70
70
ns
1
Last data in to new col. address delay
tCDL(min)
1
CLK
2
Last data in to row precharge
tRDL(min)
1
CLK
2
Last data in to burst stop
tBDL(min)
1
CLK
2
Col. address to col. address delay
tCCD(min)
1
CLK
3
Block write data-in to PRE command delay
tBPL(min)
1
CLK
Block write cycle time
tBWC(min)
1
CLK
1, 3
Number of valid output data
CAS latency=3
2
CLK
4
CAS latency=2
1


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