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74LVT16500ADGG Fiches technique(PDF) 11 Page - NXP Semiconductors |
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74LVT16500ADGG Fiches technique(HTML) 11 Page - NXP Semiconductors |
11 / 19 page 74LVT16500A_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 03 — 29 May 2006 11 of 19 Philips Semiconductors 74LVT16500A 3.3 V 18-bit universal bus transceiver; 3-state [1] All typical values are measured at VCC = 3.3 V and Tamb = 25 °C. 11. Waveforms th(H) hold time HIGH An to CPAB or Bn to CPBA see Figure 10 00- ns An to LEAB or Bn to LEBA see Figure 10 00- ns th(L) hold time LOW An to CPAB or Bn to CPBA see Figure 10 00- ns An to LEAB or Bn to LEBA see Figure 10 00- ns tWH pulse width HIGH CPAB or CPBA see Figure 6 1.2 0.8 - ns LEAB or LEBA see Figure 7 1.2 0.8 - ns tWL pulse width LOW CPAB or CPBA see Figure 6 1.2 0.8 - ns fmax maximum input clock frequency see Figure 6 150 350 - MHz Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11. Symbol Parameter Conditions Min Typ Max Unit Measurements points are given in Table 8. VOL and VOH are typical voltage output drop that occur with the output load. Fig 5. Propagation delay input (An, Bn) to output (Bn, An) in transparent mode 001aad308 output Bn or An input An or Bn VM VM tPHL tPLH VM VM VOH VI 0 V VOL |
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