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74AUP1G57GF Fiches technique(PDF) 4 Page - NXP Semiconductors |
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74AUP1G57GF Fiches technique(HTML) 4 Page - NXP Semiconductors |
4 / 22 page 74AUP1G57 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 20 July 2010 4 of 22 NXP Semiconductors 74AUP1G57 Low-power configurable multiple function gate 7.1 Logic configurations Table 5. Function selection table Logic function Figure 2-input AND see Figure 5 2-input AND with both inputs inverted see Figure 8 2-input NAND with inverted input see Figure 6 and Figure 7 2-input OR with inverted input see Figure 6 and Figure 7 2-input NOR see Figure 8 2-input NOR with both inputs inverted see Figure 5 2-input XNOR see Figure 9 Inverter see Figure 10 Buffer see Figure 11 Fig 5. 2-input AND gate or 2-input NOR gate with both inputs inverted Fig 6. 2-input NAND gate with input B inverted or 2-input OR gate with inverted C input 001aab584 B B6 Y C 1 5 2 4 3Y Y C B C VCC 001aab585 B B6 Y C 1 5 2 4 3Y Y C B C VCC Fig 7. 2-input NAND gate with input C inverted or 2-input OR gate with inverted A input Fig 8. 2-input NOR gate or 2-input AND gate with both inputs inverted 001aab586 A A 6 Y C 1 5 2 4 3Y Y C A C VCC 001aab587 A 6C 1 5 2 4 3Y VCC A Y C Y A C Fig 9. 2-input XNOR gate Fig 10. Inverter 001aab588 B6 C 1 5 2 4 3Y VCC Y B C 001aab589 A A 6 Y 1 5 2 4 3Y VCC |
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