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TPS54418 Fiches technique(PDF) 2 Page - Texas Instruments

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No de pièce TPS54418
Description  2.95 V to 6 V Input, 4 A Output, 2MHz, Synchronous Step Down Switcher With Integrated FETs ( SWIFT??
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI - Texas Instruments

TPS54418 Fiches technique(HTML) 2 Page - Texas Instruments

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TPS54418
SLVS946A – MAY 2009 – REVISED MAY 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
TJ
PACKAGE
PART NUMBER
–40°C to 150°C
3 × 3 mm QFN
TPS54418RTE
ABSOLUTE MAXIMUM RATINGS
VALUE
UNIT
Input voltage
VIN
–0.3 to 7
V
EN
–0.3 to 7
BOOT
PH + 8
VSENSE
–0.3 to 3
COMP
–0.3 to 3
PWRGD
–0.3 to 7pau
SS
–0.3 to 3
RT/CLK
–0.3 to 6
Output voltage
BOOT-PH
8
V
PH
–0.6 to 7
PH 10 ns Transient
–2 to 7
Source current
EN
100
mA
RT/CLK
100
mA
Sink current
COMP
100
mA
PWRGD
10
mA
SS
100
mA
Electrostatic discharge (HBM)
2
kV
Electrostatic discharge (CDM)
500
V
Operating Junction temperature, Tj
–40 to 150
°C
Storage temperature, Tstg
–65 to 150
°C
PACKAGE DISSIPATION RATINGS
(1) (2) (3)
over operating free-air temperature range (unless otherwise noted)
THERMAL IMPEDANCE
fJT THERMAL CHARACTERISTIC
PACKAGE
JUNCTION TO AMBIENT
JUNCTION TO TOP
RTE
37°C/W
1°C/W
(1)
Maximum power dissipation may be limited by overcurrent protection
(2)
Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C. This is the point where
distortion starts to substantially increase. Thermal management of the PCB should strive to keep the junction temperature at or below
150°C for best performance and long-term reliability. See power dissipation estimate in application section of this data sheet for more
information.
(3)
Test boards conditions:
(a) 2 inches x 2 inches, 4 layers, thickness: 0.062 inch
(b) 2 oz. copper traces located on the top of the PCB
(c) 2 oz. copper ground planes on the 2 internal layers and bottom layer
(d) 4 thermal vias (10mil) located under the device package
2
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Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS54418


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