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TL16C2550RHBG4 Fiches technique(PDF) 4 Page - Texas Instruments |
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TL16C2550RHBG4 Fiches technique(HTML) 4 Page - Texas Instruments |
4 / 47 page www.ti.com DEVICE INFORMATION TL16C2550 SLWS161D – JUNE 2005 – REVISED OCTOBER 2006 TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NAME PFB NO. FN NO. RHB NO. A0 28 31 20 I Address 0 select bit. Internal registers address selection A1 27 30 19 I Address 1 select bit. Internal registers address selection A2 26 29 18 I Address 2 select bit. Internal registers address selection Carrier detect (active low). These inputs are associated with individual UART channels A and B. A low on these pins indicates that a carrier has CDA, CDB 40, 16 42, 21 – I been detected by the modem for that channel. The state of these inputs is reflected in the modem status register (MSR). Chip select A and B (active low). These pins enable data transfers between the user CPU and the TL16C2550 for the channel(s) addressed. Individual CSA, CSB 10, 11 16, 17 7, 8 I UART sections (A, B) are addressed by providing a low on the respective CSA and CSB pins. Clear to send (active low). These inputs are associated with individual UART channels A and B. A logic low on the CTS pins indicates the modem CTSA, or data set is ready to accept transmit data from the 2550. Status can be 38, 23 40, 28 25, 16 I CTSB tested by reading MSR bit 4. These pins only affect the transmit and receive operations when auto CTS function is enabled through the enhanced feature register (EFR) bit 7, for hardware flow control operation. D0-D4 44 - 48 2 - 6 27 - 31 Data bus (bidirectional). These pins are the eight bit, 3-state data bus for transferring information to or from the controlling CPU. D0 is the least I/O significant bit and the first data bit in a transmit or receive serial data D5-D7 1 - 3 7 - 9 32, 1, 2 stream. Data set ready (active low). These inputs are associated with individual DSRA, UART channels A and B. A logic low on these pins indicates the modem or 39, 20 41, 25 – I DSRB data set is powered on and is ready for data exchange with the UART. The state of these inputs is reflected in the modem status register (MSR). Data terminal ready (active low). These outputs are associated with individual UART channels A and B. A logic low on these pins indicates that DTRA, theTLl16C2550 is powered on and ready. These pins can be controlled 34, 35 37, 38 – O DTRB through the modem control register. Writing a 1 to MCR bit 0 sets the DTR output to low, enabling the modem. The output of these pins is high after writing a 0 to MCR bit 0, or after a reset. GND 17 22 13 Signal and power ground. Interrupt A and B (active high). These pins provide individual channel interrupts, INT A and B. INT A and B are enabled when MCR bit 3 is set to INTA, a logic 1, interrupt sources are enabled in the interrupt enable register 30, 29 33, 32 22, 21 O INTB (IER). Interrupt conditions include: receiver errors, available receiver buffer data, available transmit buffer space or when a modem status flag is detected. INTA-B are in the high-impedance state after reset. Read input (active low strobe). A high to low transition on IOR will load the IOR 19 24 14 I contents of an internal register defined by address bits A0-A2 onto the TL16C2550 data bus (D0-D7) for access by an external CPU. Write input (active low strobe). A low to high transition on IOW will transfer IOW 15 20 12 I the contents of the data bus (D0-D7) from the external CPU to an internal register that is defined by address bits A0-A2 and CSA and CSB 12, 24, 25, NC – 9, 17 No internal connection 37 User defined outputs. This function is associated with individual channels A and B. The state of these pins is defined by the user through the software settings of the MCR register, bit 3. INTA-B are set to active mode and OP OPA, OPB 32, 9 35, 15 – O to a logic 0 when the MCR-3 is set to a logic 1. INTA-B are set to the 3-state mode and OP to a logic 1 when MCR-3 is set to a logic 0. See bit 3, modem control register (MCR bit 3). The output of these two pins is high after reset. Reset. RESET will reset the internal registers and all the outputs. The UART transmitter output and the receiver input will be disabled during reset RESET 36 39 24 I time. See TL16C2550 external reset conditions for initialization details. RESET is an active-high input. 4 Submit Documentation Feedback |
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