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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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AM1806BZCE3 Fiches technique(PDF) 27 Page - Texas Instruments |
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AM1806BZCE3 Fiches technique(HTML) 27 Page - Texas Instruments |
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27 / 243 page  AM1806 www.ti.com SPRS658B – FEBRUARY 2010 – REVISED MAY 2010 3.7.7 Serial Peripheral Interface Modules (SPI) Table 3-9. Serial Peripheral Interface (SPI) Terminal Functions SIGNAL POWER TYPE(1) PULL(2) DESCRIPTION GROUP(3) NAME NO. SPI0 SPI0_CLK / EPWM0A / GP1[8] D19 I/O CP[7] A SPI0 clock SPI0_ENA / EPWM0B / PRU0_R30[6] C17 I/O CP[7] A SPI0 enable SPI0_SCS[0] / TM64P1_OUT12 / GP1[6] / TM64P1_IN12 D17 I/O CP[10] A SPI0_SCS[1] / TM64P0_OUT12 / GP1[7] / TM64P0_IN12 E16 I/O CP[10] A SPI0_SCS[2] / UART0_RTS / GP8[1] D16 I/O CP[9] A SPI0 chip selects SPI0_SCS[3] / UART0_CTS / GP8[2] E17 I/O CP[9] A SPI0_SCS[4] / UART0_TXD / GP8[3] D18 I/O CP[8] A SPI0_SCS[5] / UART0_RXD / GP8[4] C19 I/O CP[8] A SPI0 data SPI0_SIMO / EPWMSYNCO / GP8[5] C18 I/O/Z CP[7] A slave-in-master-out SPI0 data SPI0_SOMI / EPWMSYNCI / GP8[6] C16 I/O/Z CP[7] A slave-out-master-in SPI1 SPI1_CLK / GP2[13] G19 I/O CP[15] A SPI1 clock SPI1_ENA / GP2[12] H16 I/O CP[15] A SPI1 enable SPI1_SCS[0] / EPWM1B / PRU0_R30[8] / GP2[14] / TM64P3_IN12 E19 I/O CP[14] A SPI1_SCS[1] / EPWM1A / PRU0_R30[7] / GP2[15] / TM64P2_IN12 F18 I/O CP[14] A SPI1_SCS[2] / UART1_TXD / GP1[0] F19 I/O CP[13] A SPI1_SCS[3] / UART1_RXD / GP1[1] E18 I/O CP[13] A SPI1 chip selects SPI1_SCS[4] / UART2_TXD / I2C1_SDA /GP1[2] F16 I/O CP[12] A SPI1_SCS[5] / UART2_RXD / I2C1_SCL /GP1[3] F17 I/O CP[12] A SPI1_SCS[6] / I2C0_SDA / TM64P3_OUT12 / GP1[4] G18 I/O CP[11] A SPI1_SCS[7] / I2C0_SCL / TM64P2_OUT12 / GP1[5] G16 I/O CP[11] A SPI1 data SPI1_SIMO / GP2[10] G17 I/O/Z CP[15] A slave-in-master-out SPI1 data SPI1_SOMI / GP2[11] H17 I/O/Z CP[15] A slave-out-master-in (1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a pull-up, an external pull-up can be used. (3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power supply DVDD3318_C. Copyright © 2010, Texas Instruments Incorporated Device Overview 27 Submit Documentation Feedback Product Folder Link(s): AM1806 |
Numéro de pièce similaire - AM1806BZCE3 |
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Description similaire - AM1806BZCE3 |
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