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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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AM1707BZKBA3 Fiches technique(PDF) 48 Page - Texas Instruments |
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AM1707BZKBA3 Fiches technique(HTML) 48 Page - Texas Instruments |
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48 / 199 page  0.1 µF 0.01 µF 50R 1.14V-1.32V 50R VSS PLL0_VDDA PLL0_VSSA FerriteBead:MurataBLM31PG500SN1L orEquivalent AM1707 SPRS637A – FEBRUARY 2010 – REVISED APRIL 2010 www.ti.com 6.7 Clock PLLs The device has one PLL controller that provides clock to different parts of the system. PLL0 provides clocks (though various dividers) to most of the components of the device. The PLL controller provides the following: • Glitch-Free Transitions (on changing clock settings) • Domain Clocks Alignment • Clock Gating • PLL power down The various clock outputs given by the controller are as follows: • Domain Clocks: SYSCLK [1:n] • Auxiliary Clock from reference clock source: AUXCLK Various dividers that can be used are as follows: • Post-PLL Divider: POSTDIV • SYSCLK Divider: D1, ¼, Dn Various other controls supported are as follows: • PLL Multiplier Control: PLLM • Software programmable PLL Bypass: PLLEN 6.7.1 PLL Device-Specific Information The PLL requires some external filtering components to reduce power supply noise as shown in Figure 6-8. Figure 6-8. PLL External Filtering Components The input to the PLL is either from the on-chip oscillator (OSCIN pin) or from an external clock on the CLKIN pin. The PLL outputs seven clocks that have programmable divider options. Figure 6-9 illustrates the PLL Topology. The PLL is disabled by default after a device reset. It must be configured by software according to the allowable operating conditions listed in Table 6-5 before enabling the processor to run from the PLL by setting PLLEN = 1. 48 Peripheral Information and Electrical Specifications Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1707 |
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Description similaire - AM1707BZKBA3 |
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