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CDCE706PWR Fiches technique(PDF) 4 Page - Texas Instruments |
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CDCE706PWR Fiches technique(HTML) 4 Page - Texas Instruments |
4 / 40 page 5x6-Switch A InputCLK (PLL Bypass) PLL1 PLL3 6x6-SwitchB 7-BitDivider Y0 Y1 Y2 Y3 Y4 Y5 P0 P1 P2 P3 P4 P5 Programming PLL2 Non-SSC PLL2 w/SSC B0335-01 CDCE706 SCAS815I – OCTOBER 2005 – REVISED NOVEMBER 2008 ........................................................................................................................................... www.ti.com OUTPUT SWITCH MATRIX TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION TSSOP20 NAME NO. Dependent on SMBus settings, CLK_IN0 is the crystal-oscillator input and can also be used as an CLK_IN0 5 I LVCMOS input or as positive differential signal inputs. Depending on SMBus settings, CLK_IN1 serves as the crystal oscillator output or can be the CLK_IN1 6 I/O second LVCMOS input or the negative differential signal input. GND 4, 8, 13, 17 Ground Ground User-programmable control input S0 (PLL bypass or power-down mode) or A0 (address bit 0), or S0, A0, 1 I CLK_SEL (selects one of two LVCMOS clock inputs), dependent on the SMBus settings; LVCMOS CLK_SEL inputs; internal pullup 150 k Ω User-programmable control input S1 (output enable/disable or all output low), A1 (address bit 1), S1, A1 2 I dependent on the SMBus settings; LVCMOS inputs; internal pullup 150 k Ω SCLOCK 10 I Serial control clock input for SMBus controller; LVCMOS input SDATA 9 I/O Serial control data input/output for SMBus controller; LVCMOS input VCC 3, 7 Power 3.3-V power supply for the device VCCOUT1 14 Power Power supply for outputs Y0, Y1 VCCOUT2 18 Power Power supply for outputs Y2, Y3, Y4, Y5 11, 12, 15, Y0 to Y5 O LVCMOS outputs 16, 19, 20 4 Submit Documentation Feedback Copyright © 2005–2008, Texas Instruments Incorporated Product Folder Link(s): CDCE706 |
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