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LM3S9L97-IQC20-C1T Fiches technique(PDF) 6 Page - Texas Instruments

No de pièce LM3S9L97-IQC20-C1T
Description  Stellaris짰 LM3S9L97 Microcontroller
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI - Texas Instruments

LM3S9L97-IQC20-C1T Fiches technique(HTML) 6 Page - Texas Instruments

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11.4.5 16-Bit Input Edge Timing Mode .................................................................................... 398
11.4.6 16-Bit PWM Mode ....................................................................................................... 398
11.5
Register Map .............................................................................................................. 399
11.6
Register Descriptions .................................................................................................. 400
12
Watchdog Timers ................................................................................................. 432
12.1
Block Diagram ............................................................................................................ 433
12.2
Functional Description ................................................................................................. 433
12.2.1 Register Access Timing ............................................................................................... 434
12.3
Initialization and Configuration ..................................................................................... 434
12.4
Register Map .............................................................................................................. 434
12.5
Register Descriptions .................................................................................................. 435
13
Analog-to-Digital Converter (ADC) ..................................................................... 457
13.1
Block Diagram ............................................................................................................ 458
13.2
Signal Description ....................................................................................................... 459
13.3
Functional Description ................................................................................................. 460
13.3.1 Sample Sequencers .................................................................................................... 460
13.3.2 Module Control ............................................................................................................ 461
13.3.3 Hardware Sample Averaging Circuit ............................................................................. 464
13.3.4 Analog-to-Digital Converter .......................................................................................... 464
13.3.5 Differential Sampling ................................................................................................... 466
13.3.6 Internal Temperature Sensor ........................................................................................ 469
13.3.7 Digital Comparator Unit ............................................................................................... 469
13.4
Initialization and Configuration ..................................................................................... 474
13.4.1 Module Initialization ..................................................................................................... 474
13.4.2 Sample Sequencer Configuration ................................................................................. 475
13.5
Register Map .............................................................................................................. 475
13.6
Register Descriptions .................................................................................................. 477
14
Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 535
14.1
Block Diagram ............................................................................................................ 536
14.2
Signal Description ....................................................................................................... 536
14.3
Functional Description ................................................................................................. 538
14.3.1 Transmit/Receive Logic ............................................................................................... 538
14.3.2 Baud-Rate Generation ................................................................................................. 539
14.3.3 Data Transmission ...................................................................................................... 540
14.3.4 Serial IR (SIR) ............................................................................................................. 540
14.3.5 ISO 7816 Support ....................................................................................................... 541
14.3.6 Modem Handshake Support ......................................................................................... 541
14.3.7 LIN Support ................................................................................................................ 543
14.3.8 FIFO Operation ........................................................................................................... 544
14.3.9 Interrupts .................................................................................................................... 544
14.3.10 Loopback Operation .................................................................................................... 545
14.3.11 DMA Operation ........................................................................................................... 545
14.4
Initialization and Configuration ..................................................................................... 546
14.5
Register Map .............................................................................................................. 547
14.6
Register Descriptions .................................................................................................. 548
15
Synchronous Serial Interface (SSI) .................................................................... 597
15.1
Block Diagram ............................................................................................................ 598
June 15, 2010
6
Texas Instruments-Advance Information
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