CDCEL925PW datasheet(7/27 Pages) TI

No de pièce	CDCEL925PW

Description	PROGRAMMABLE 2-PLL VCXO CLOCK SYNTHESIZER WITH 1.8-V, 2.5-V and 3.3-V LVCMOS OUTPUTS

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Fabricant	TI [Texas Instruments]

Site Internet	http://www.ti.com

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CDCE925

CDCEL925

www.ti.com

SCAS847F – JULY 2007 – REVISED MARCH 2010

DEVICE CHARACTERISTICS (continued)

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP(1)

MAX

UNIT

1 PLL switching, Y2-to-Y3

50

70

tjit(cc)

Cycle-to-cycle jitter (6) (7)

ps

2 PLL switching, Y2-to-Y5

90

130

1 PLL switching, Y2-to-Y3

60

100

tjit(per)

Peak-to-peak period jitter (7)

ps

2 PLL switching, Y2-to-Y5

100

160

fOUT = 50 MHz; Y1-to-Y3

70

tsk(o)

Output skew (8)

ps

fOUT = 50 MHz; Y2-to-Y5

150

odc

Output duty cycle (9)

fVCO = 100 MHz; Pdiv = 1

45%

55%

CDCEL925 — LVCMOS PARAMETER for VDDOUT = 1.8 V – Mode

VDDOUT = 1.7 V, IOH = –0.1 mA

1.6

VOH

LVCMOS high-level output voltage

VDDOUT = 1.7 V, IOH = –4 mA

1.4

V

VDDOUT = 1.7 V, IOH = –8 mA

1.1

VDDOUT = 1.7 V, IOL = 0.1 mA

0.1

VOL

LVCMOS low-level output voltage

VDDOUT = 1.7 V, IOL = 4 mA

0.3

V

VDDOUT = 1.7 V, IOL = 8 mA

0.6

tPLH, tPHL

Propagation delay

All PLL bypass

2.6

ns

tr/tf

Rise and fall time

VDDOUT = 1.8 V (20%–80%)

0.7

ns

1 PLL switching, Y2-to-Y3

80

110

tjit(cc)

Cycle-to-cycle jitter (6) (7)

ps

2 PLL switching, Y2-to-Y5

130

200

1 PLL switching, Y2-to-Y3

100

130

tjit(per)

Peak-to-peak period jitter (10)

ps

2 PLL switching, Y2-to-Y5

150

220

fOUT = 50 MHz; Y1-to-Y3

50

tsk(o)

Output skew (11)

ps

fOUT = 50 MHz; Y2-to-Y5

110

odc

Output duty cycle (12)

fVCO = 100 MHz; Pdiv = 1

45%

55%

SDA/SCL PARAMETER

VIK

SCL and SDA input clamp voltage

VDD = 1.7 V; II = –18 mA

–1.2

V

IIH

SCL and SDA input current

VI = VDD; VDD = 1.9 V

±10

mA

VIH

SDA/SCL input high voltage(13)

0.7 VDD

V

VIL

SDA/SCL input low voltage(13)

0.3 VDD

V

VOL

SDA low-level output voltage

IOL = 3 mA VDD = 1.7 V

0.2 VDD

V

CI

SCL/SDA Input capacitance

VI = 0 V or VDD

3

10

pF

(6)

10000 cycles.

(7)

Jitter depends on configuration. Jitter data is for input frequency = 27 MHz, fVCO = 135 MHz, fOUT = 27 MHz. fOUT = 3.072 MHz or input

frequency = 27 MHz, fVCO = 108 MHz, fOUT = 27 MHz. fOUT = 16.384 MHz, fOUT = 25 MHz, fOUT = 74.25 MHz, fOUT = 48 MHz

(8)

The tsk(o) specification is only valid for equal loading of each bank of outputs, and the outputs are generated from the same divider,

data sampled on rising edge (tr).

(9)

odc depends on output rise- and fall time (tr/tf);

(10) Jitter depends on configuration. Jitter data is for input frequency = 27 MHz, fVCO = 135 MHz, fOUT = 27 MHz. fOUT = 3.072 MHz or input

frequency = 27 MHz, fVCO = 108 MHz, fOUT = 27 MHz. fOUT = 16.384 MHz, fOUT = 25 MHz, fOUT = 74.25 MHz, fOUT = 48 MHz

(11) The tsk(o) specification is only valid for equal loading of each bank of outputs, and the outputs are generated from the same divider,

data sampled on rising edge (tr).

(12) odc depends on output rise- and fall time (tr/tf);

(13) SDA and SCL pins are 3.3 V tolerant.

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