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SN74AUC2G53 Fiches technique(PDF) 2 Page - Texas Instruments |
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SN74AUC2G53 Fiches technique(HTML) 2 Page - Texas Instruments |
2 / 20 page Y2 A INH Y1 COM 5 2 7 6 1 SW SW NOTE A: For simplicity, the test conditions shown in Figures 1 through 4 and 6 through 10 are for the demultiplexer configuration. Signals may be passed from COM to Y1 (Y2) or from Y1 (Y2) to COM. COM Y SN74AUC2G53 SCES484C – AUGUST 2003 – REVISED JANUARY 2009 ................................................................................................................................................ www.ti.com ORDERING INFORMATION TA PACKAGE(1)(2) ORDERABLE PART NUMBER TOP-SIDE MARKING(3) NanoFree™ – WCSP (DSBGA) Reel of 3000 SN74AUC2G53YZPR _ _ _U4_ 0.23-mm Large Bump – YZP (Pb-free) –40C to 85C SSOP – DCT Reel of 3000 SN74AUC2G53DCTR U53_ _ _ VSSOP – DCU Reel of 3000 SN74AUC2G53DCUR U53_ (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. (2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. (3) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site. DCU: The actual top-side marking has one additional character that designates the assembly/test site. YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). FUNCTION TABLE CONTROL ON INPUTS CHANNEL INH A L L Y1 L H Y2 H X None LOGIC DIAGRAM (POSITIVE LOGIC) SIMPLIFIED SCHEMATIC, EACH SWITCH (SW) 2 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): SN74AUC2G53 |
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