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TPS386596L33 Fiches technique(PDF) 7 Page - Texas Instruments

No de pièce TPS386596L33
Description  Quad Reset Supervisor with Manual Reset Input
Download  12 Pages
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI - Texas Instruments

TPS386596L33 Fiches technique(HTML) 7 Page - Texas Instruments

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background image
RP
RSL2
RSL3
RSH2
RSH3
TPS386596
SENSE1
SENSE3
SENSE2
VCC
GND
DSP
CPU
FPGA
RESET
____
RESET
____
DC-DC
LDO
DC-DC
LDO
DC-DC
LDO
VCC1
VCC3
VCC2
VIN
DC-DC
LDO
3.3V
SENSE4
VCC4
RSL4
RSH4
Sub CPU
MSP430
MR
__
TPS386596L33
www.ti.com
SLVSA75 – JULY 2010
Figure 4. Typical TPS386596L33 Application Diagram
MANUAL RESET
The manual reset MR input allows external logic signal from processors, other logic circuits, and/or discrete
sensors to initiate a reset. The typical application of a TPS386596 has its RESET output connected to processor.
A logic low at MR causes RESET to assert. After MR returns to a logic high and SENSEn are above their
respective voltage thresholds, RESET is released after a fixed 50ms reset delay time. An internal 100k
Ω pull-up
to VCC is integrated on the MR input. There is also an internal 50ns (typical) deglitch circuit.
Table 1. RESET Truth Table
CONDITION
OUTPUT
MR = L
SENSEn < VITn
RESET = L
Reset asserted
MR = L
SENSEn > VITn
RESET = L
Reset asserted
MR = H
SENSE1 < VIT1 OR
RESET = L
Reset asserted
SENSE2 < VIT2 OR
SENSE3 < VIT3 OR
SENSE4 < VIT4
MR = H
SENSE1 > VIT1 AND
RESET = H
Reset released
SENSE2 > VIT2 AND
SENSE3 > VIT3 AND
SENSE4 > VIT4
IMMUNITY TO SENSE PIN VOLTAGE TRANSIENTS
The TPS386596 is relatively immune to short negative transients on the SENSEn pins. Sensitivity to transients is
dependent on how much percentage the sense voltage drops below the threshold voltage, as shown in Figure 8.
See Figure 5 for the measurement technique.
Copyright © 2010, Texas Instruments Incorporated
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