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TPS40210SHKK Fiches technique(PDF) 5 Page - Texas Instruments |
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TPS40210SHKK Fiches technique(HTML) 5 Page - Texas Instruments |
5 / 39 page 0 1 10 100 1000 110 130 150 170 190 210 230 Continuous TJ (°C) Electromigration Fail Mode TPS40210-HT www.ti.com SLVSAD8 – JUNE 2010 ELECTRICAL CHARACTERISTICS (continued) TJ = –55°C to 210°C, VVDD= 12 Vdc, all parameters at zero power dissipation (unless otherwise noted) TA = –55°C to 125°C TA = 210°C PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX Overcurrent reset VSS(rst) threshold voltage (at 100 150 350 100 150 350 mV SS pin) Leading edge TBLNK 75 ns blanking Current-Sense Amplifier Current sense ACS 4.2 5.6 7.2 4 4.8 7.2 V/V amplifier gain IB(ISNS) Input bias current 1 3 1 3 mA Driver Gate driver source IGDRV(src) VGDRV = 4 V, TJ = 25°C 280 335 180 280 mA current Gate driver sink IGDRV(snk) VGDRV = 4 V, TJ = 25°C 300 330 230 290 mA current Linear Regulator Bypass voltage VBP 0 mA < IBP < 15 mA 7 8 9 4.8 8.45 10 V output Disable/Enable VDIS(en) Turn-on voltage 0.7 1 1.3 0.7 1 1.3 V VDIS(hys) Hysteresis voltage 25 145 220 25 155 220 mV DIS pin pulldown RDIS 0.7 1.1 1.5 0.5 0.9 1.5 M Ω resistance Notes: 1. See datasheet for absolute maximum and minimum recommended operating conditions. 2. Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect life). Figure 1. TPS40210SKGD1/TPS40210SHKK Operating Life Derating Chart Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): TPS40210-HT |
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