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CAT150021MWI-GT3 Fiches technique(PDF) 8 Page - ON Semiconductor

No de pièce CAT150021MWI-GT3
Description  Voltage Supervisor with 2-Kb and 4-Kb SPI Serial CMOS EEPROM
Download  15 Pages
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Fabricant  ONSEMI [ON Semiconductor]
Site Internet  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

CAT150021MWI-GT3 Fiches technique(HTML) 8 Page - ON Semiconductor

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CAT15002, CAT15004
Doc. No. MD-1126 Rev. B
8
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
WRITE OPERATIONS
The CAT15002/04 device powers up into a write disable
state. The device contains a Write Enable Latch (WEL)
which must be set before attempting to write to the
memory array or to the status register. In addition, the
address of the memory location(s) to be written must be
outside the protected area, as defined by BP0 and BP1
bits from the status register.
Write Enable and Write Disable
The internal Write Enable Latch and the corresponding
Status Register WEL bit are set by sending the WREN
instruction to the CAT15002/04. Care must be taken to
take the CS
¯¯ input high after the WREN instruction, as
otherwise the Write Enable Latch will not be properly
set. WREN timing is illustrated in Figure 4. The WREN
instruction must be sent prior any WRITE or WRSR
instruction.
The internal write enable latch is reset by sending the
WRDI instruction as shown in Figure 5. Disabling write
operations by resetting the WEL bit, will protect the
device against inadvertent writes.
Figure 4. WREN Timing
Note: Dashed Line = mode (1, 1) - - - - - -
Figure 5. WRDI Timing
Note: Dashed Line = mode (1, 1) - - - - - -
SCK
SI
CS
SO
000
0
0
11
0
HIGH IMPEDANCE
SCK
SI
CS
SO
0
0
000
10
0
HIGH IMPEDANCE


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