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TPS7A8018 Fiches technique(PDF) 6 Page - Texas Instruments |
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TPS7A8018 Fiches technique(HTML) 6 Page - Texas Instruments |
6 / 20 page IN NR IN EN 6 7 8 5 4 OUT OUT FB/SNS GND 1 2 3 TPS7A80xx SBVS135A – JUNE 2010 – REVISED JUNE 2010 www.ti.com PIN CONFIGURATION DRB PACKAGE 3mm x 3mm SON-8 (TOP VIEW) Table 1. PIN DESCRIPTIONS NAME PIN NO. DESCRIPTION IN 7, 8 Unregulated input supply. GND 4, pad Ground. Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown EN 5 mode. Refer to Shutdown in the Application Information section for more details. EN must not be left floating and can be connected to IN if not used. Connect an external capacitor between this pin and ground to reduce output noise to very low levels. Also, NR 6 the capacitor slows down the VOUT ramp (RC softstart). Adjustable voltage version only. This pin is the input to the control loop error amplifier and is used to set FB 3 the output voltage of the device. Fixed voltage versions only. This pin is the input to the control loop error amplifier and is used to set the SNS 3 output voltage of the device. This pin is to be shorted to OUT at load devices. OUT 1, 2 Regulator output. A 4.7mF or larger capacitor of any type is required for stability. 6 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated |
Numéro de pièce similaire - TPS7A8018 |
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Description similaire - TPS7A8018 |
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