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CS8415A Fiches technique(PDF) 8 Page - Cirrus Logic |
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CS8415A Fiches technique(HTML) 8 Page - Cirrus Logic |
8 / 46 page 8 DS470F4 CS8415A SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS Inputs: Logic 0 = 0 V, Logic 1 = VL+; CL = 20 pF. 7. The active edges of OSCLK are programmable. 8. The polarity OLRCK is programmable. 9. No more than 128 SCLK per frame. 10. This delay is to prevent the previous OSCLK edge from being interpreted as the first one after OLRCK has changed. 11. This setup time ensures that this OSCLK edge is interpreted as the first one after OLRCK has changed. Parameter Symbol Min Typ Max Units OSCLK Active Edge to SDOUT Output Valid (Note 7) tdpd - - 20 ns Master Mode RMCK to OSCLK active edge delay (Note 7) tsmd 0 - 10 ns RMCK to OLRCK delay (Note 8) tlmd 0 - 10 ns OSCLK and OLRCK Duty Cycle -50 - % Slave Mode OSCLK Period (Note 9) tsckw 36 - - ns OSCLK Input Low Width tsckl 14 - - ns OSCLK Input High Width tsckh 14 - - ns OSCLK Active Edge to OLRCK Edge (Note 7, 8, 10) tlrckd 20 - - ns OLRCK Edge Setup Before OSCLK Active Edge Notes 7, 8, 11 tlrcks 20 - - ns t sm d t lm d Ha rd wa re M o d e S o ftw are M ode OS C L K (output) OL RCK (output) RM CK (output) RM CK (output) sckh sckl sckw t t t tdpd SDOUT (input) (input) lrcks t lrckd t OSCLK OLRCK Figure 1. Audio Port Master Mode Timing Figure 2. Audio Port Slave Mode and Data Input Timing |
Numéro de pièce similaire - CS8415A_05 |
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Description similaire - CS8415A_05 |
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