ADC0808S125_ADC0808S250_3

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 03 — 24 February 2009

7 of 23

NXP Semiconductors

ADC0808S125/250

Single 8-bit ADC, up to 125 MHz or 250 MHz

7.3 Timing output

7.4 Timing complete conversion signal

The ADC0808S generates an adjustable clock output signal on pin CCS called Complete

Conversion Signal, which can be used to control the acquisition of converted output data

to the digital circuit connected to the ADC0808S output data bus.

Two logic input pins DEL0 and DEL1 control the delay of the edge of the CCS signal to

achieve an optimal position in the stable, usable zone of the data as shown in Figure 6.

Pin CCSSEL selects the CCS frequency; see Table 8.

Fig 5.

Output timing diagram (CCS not selected)

IN, INN

CLK+, CLK

−

n

D0 to D7

50 %

data

n

− 2n − 1

data

data

data

n

+ 1

n

001aab892

sample

n

sample

n

+ 1

sample

n

+ 2

sample

n

+ 3

sample

n

+ 4

Table 7.

Complete conversion signal selection

Pin DEL0

Pin DEL1

Pin CCS

LOW

LOW

high-impedance

HIGH

LOW

active; see Table 13

LOW

HIGH

HIGH

HIGH

Table 8.

Complete conversion signal frequency selection

Pin CCSSEL

HIGH or not connected

LOW