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74LVCH16374ADGG Fiches technique(PDF) 6 Page - NXP Semiconductors

No de pièce 74LVCH16374ADGG
Description  16-bit edge-triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-state
Download  19 Pages
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Fabricant  NXP [NXP Semiconductors]
Site Internet  http://www.nxp.com
Logo NXP - NXP Semiconductors

74LVCH16374ADGG Fiches technique(HTML) 6 Page - NXP Semiconductors

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74LVC_LVCH16374A_7
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 07 — 23 March 2010
6 of 19
NXP Semiconductors
74LVC16374A; 74LVCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
5.2 Pin description
6.
Functional description
[1]
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition;
↑ = LOW-to-HIGH transition;
Z = high-impedance OFF-state.
7.
Limiting values
Table 2.
Pin description
Symbol
Pin
Description
SOT370-1 and SOT362-1
SOT1134-1
1OE, 2OE
1, 24
A30, A13
output enable input (active LOW)
GND
4, 10, 15, 21, 28, 34, 39, 45
A32, A3, A8, A11, A16, A19, A24, A27
ground (0 V)
VCC
7, 18, 31, 42
A1, A10, A17, A26
supply voltage
1Q0 to 1Q7 2, 3, 5, 6, 8, 9, 11, 12
B20, A31, D5, D1, A2, B2, B3, A5
data output
2Q0 to 2Q7 13, 14, 16, 17, 19, 20, 22, 23
A6, B5, B6, A9, D2, D6, A12, B8
data output
1D0 to 1D7 47, 46, 44, 43, 41, 40, 38, 37
B18, A28, D8, D4, A25, B16, B15, A22 data input
2D0 to 2D7 36, 35, 33, 32, 30, 29, 27, 26
A21, B13, B12, A18, D3, D7, A15, B10 data input
1CP, 2CP
48, 25
A29, A14
clock input
Table 3.
Function selection[1]
Operating mode
Input
Internal flip-flop
Output nQ0 to nQ7
nOE
nCP
nDn
Load and read register
L
lL
L
L
hH
H
Load register and disable outputs
H
lL
Z
H
hH
Z
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Max
Unit
VCC
supply voltage
−0.5
+6.5
V
IIK
input clamping current
VI <0V
−50
-
mA
VI
input voltage
[1]
−0.5
+6.5
V
IOK
output clamping current
VO >VCC or VO <0V
-
±50
mA
VO
output voltage
output HIGH-or LOW-state
[2]
−0.5
VCC +0.5
V
output 3-state
[2]
−0.5
+6.5
V
IO
output current
VO =0 VtoVCC
-
±50
mA
ICC
supply current
-
100
mA
IGND
ground current
−100
-
mA
Tstg
storage temperature
−65
+150
°C


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