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74LVC2G38GD Fiches technique(PDF) 8 Page - NXP Semiconductors |
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74LVC2G38GD Fiches technique(HTML) 8 Page - NXP Semiconductors |
8 / 16 page 74LVC2G38_7 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 07 — 20 March 2009 8 of 16 NXP Semiconductors 74LVC2G38 Dual 2-input NAND gate; open drain Table 9. Measurement points Supply voltage Input Output VCC VM VX VM 1.65 V to 1.95 V 0.5 × V CC VOL + 0.15 V 0.5 × V CC 2.3 V to 2.7 V 0.5 × V CC VOL + 0.15 V 0.5 × V CC 2.7 V 1.5 V VOL + 0.3 V 1.5 V 3.0 V to 3.6 V 1.5 V VOL + 0.3 V 1.5 V 4.5 V to 5.5 V 0.5 × VCC VOL + 0.3 V 0.5 × V CC Test data is given in Table 10 Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 9. Test circuit for measuring switching times VEXT VCC VI VO 001aae235 DUT CL RT RL RL PULSE GENERATOR VM VM tW tW 10 % 90 % 0 V VI VI negative pulse positive pulse 0 V VM VM 90 % 10 % tf tr tr tf Table 10. Test data Supply voltage Input Load VEXT VCC VI tr, tf CL RL tPLZ, tPZL 1.65 V to 1.95 V VCC ≤ 2.0 ns 30 pF 1 k Ω 2 × VCC 2.3 V to 2.7 V VCC ≤ 2.0 ns 30 pF 500 Ω 2 × V CC 2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω 6 V 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω 6 V 4.5 V to 5.5 V VCC ≤ 2.5 ns 50 pF 500 Ω 2 × V CC |
Numéro de pièce similaire - 74LVC2G38GD |
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