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AM1808AZWT4 Datasheet(Fiches technique) 2 Page - Texas Instruments

Numéro de pièce AM1808AZWT4
Description  AM1808 ARM Microprocessor
Télécharger  264 Pages
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
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AM1808
SPRS653A – FEBRUARY 2010 – REVISED APRIL 2010
www.ti.com
– Dedicated switched central resource
ENABLE and WAIT Controls
• USB 1.1 OHCI (Host) With Integrated PHY
• Serial ATA (SATA) Controller:
(USB1)
– Supports SATA I (1.5 Gbps) and SATA II (3.0
• USB 2.0 OTG Port With Integrated PHY (USB0)
Gbps)
– USB 2.0 High-/Full-Speed Client
– Supports all SATA Power Management
Features
– USB 2.0 High-/Full-/Low-Speed Host
– Hardware-Assisted Native Command
– End Point 0 (Control)
Queueing (NCQ) for up to 32 Entries
– End Points 1,2,3,4 (Control, Bulk, Interrupt or
– Supports Port Multiplier and
ISOC) Rx and Tx
Command-Based Switching
• One Multichannel Audio Serial Port:
• Real-Time Clock With 32 KHz Oscillator and
– Transmit/Receive Clocks
Separate Power Rail
– Two Clock Zones and 16 Serial Data Pins
• Three One 64-Bit General-Purpose Timers
– Supports TDM, I2S, and Similar Formats
(Configurable as Two 32-Bit Timers)
– DIT-Capable
• One 64-bit General-Purpose/Watchdog Timer
– FIFO buffers for Transmit and Receive
(Configurable as Two 32-bit General-Purpose
• Two Multichannel Buffered Serial Ports:
Timers)
– Transmit/Receive Clocks
• Two Enhanced Pulse Width Modulators
– Two Clock Zones and 16 Serial Data Pins
(eHRPWM):
– Supports TDM, I2S, and Similar Formats
– Dedicated 16-Bit Time-Base Counter With
Period And Frequency Control
– AC97 Audio Codec Interface
– 6 Single Edge, 6 Dual Edge Symmetric or 3
– Telecom Interfaces (ST-Bus, H100)
Dual Edge Asymmetric Outputs
– 128-channel TDM
– Dead-Band Generation
– FIFO buffers for Transmit and Receive
– PWM Chopping by High-Frequency Carrier
• 10/100 Mb/s Ethernet MAC (EMAC):
– Trip Zone Input
– IEEE 802.3 Compliant
• Three 32-Bit Enhanced Capture Modules
– MII Media Independent Interface
(eCAP):
– RMII Reduced Media Independent Interface
– Configurable as 3 Capture Inputs or 3
– Management Data I/O (MDIO) Module
Auxiliary Pulse Width Modulator (APWM)
• Video Port Interface (VPIF):
outputs
– Two 8-bit SD (BT.656), Single 16-bit or Single
– Single Shot Capture of up to Four Event
Raw (8-/10-/12-bit) Video Capture Channels
Time-Stamps
– Two 8-bit SD (BT.656), Single 16-bit Video
• 361-Ball Pb-Free Plastic Ball Grid Array (PBGA)
Display Channels
[ZCE Suffix], 0.65-mm Ball Pitch
• Universal Parallel Port (uPP):
• 361-Ball Pb-Free Plastic Ball Grid Array (PBGA)
– High-Speed Parallel Interface to FPGAs and
[ZWT Suffix], 0.80-mm Ball Pitch
Data Converters
• Commercial or Extended Temperature
– Data Width on Each of Two Channels is 8- to
• Community Resources
16-bit Inclusive
– TI E2E Community
– Single Data Rate or Dual Data Rate Transfers
– TI Embedded Processors Wiki
– Supports Multiple Interfaces with START,
2
AM1808 ARM Microprocessor
Copyright © 2010, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): AM1808




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