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AM1806ZWTA4 Fiches technique(PDF) 70 Page - Texas Instruments |
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AM1806ZWTA4 Fiches technique(HTML) 70 Page - Texas Instruments |
70 / 241 page OSCOUT OSCIN OSCVSS Clock Input toPLL NC AM1806 SPRS658B – FEBRUARY 2010 – REVISED MAY 2010 www.ti.com Figure 6-7. External 1.2V Clock Source Table 6-3. OSCIN Timing Requirements for an Externally Driven Clock PARAMETER MIN MAX UNIT fOSCIN OSCIN frequency range 12 50 MHz tc(OSCIN) Cycle time, external clock driven on OSCIN 20 ns tw(OSCINH) Pulse width high, external clock on OSCIN 0.4 tc(OSCIN) ns tw(OSCINL) Pulse width low, external clock on OSCIN 0.4 tc(OSCIN) ns tt(OSCIN) Transition time, OSCIN 0.25P (1) ns tj(OSCIN) Period jitter, OSCIN 0.02P(1) ns (1) Where P = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve noise immunity on input signals. 6.6 Clock PLLs The device has two PLL controllers that provide clocks to different parts of the system. PLL0 provides clocks (though various dividers) to most of the components of the device. PLL1 provides clocks to the mDDR/DDR2 Controller and provides an alternate clock source for the ASYNC3 clock domain. This allows the peripherals on the ASYNC3 clock domain to be immune to frequency scaling operation on PLL0. The PLL controller provides the following: • Glitch-Free Transitions (on changing clock settings) • Domain Clocks Alignment • Clock Gating • PLL power down The various clock outputs given by the controller are as follows: • Domain Clocks: SYSCLK [1:n] • Auxiliary Clock from reference clock source: AUXCLK Various dividers that can be used are as follows: • Post-PLL Divider: POSTDIV • SYSCLK Divider: D1, ¼, Dn Various other controls supported are as follows: • PLL Multiplier Control: PLLM • Software programmable PLL Bypass: PLLEN 70 Peripheral Information and Electrical Specifications Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1806 |
Numéro de pièce similaire - AM1806ZWTA4 |
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