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AM1806BZCED4 Fiches technique(PDF) 97 Page - Texas Instruments

No de pièce AM1806BZCED4
Description  AM1806 ARM Microprocessor
Download  241 Pages
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AM1806BZCED4 Fiches technique(HTML) 97 Page - Texas Instruments

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AM1806
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SPRS658B – FEBRUARY 2010 – REVISED MAY 2010
Table 6-21. Timing Requirements for EMIFA Asynchronous Memory Interface (1)
1.3V, 1.2V
1.1V
1.0V
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
READS and WRITES
E
tc(CLK)
Cycle time, EMIFA module clock
10
15
20
ns
2
tw(EM_WAIT)
Pulse duration, EM_WAIT assertion and deassertion
2E
2E
2E
ns
READS
12
tsu(EMDV-EMOEH)
Setup time, EM_D[15:0] valid before EM_OE high
3
5
7
ns
13
th(EMOEH-EMDIV)
Hold time, EM_D[15:0] valid after EM_OE high
0
0
0
ns
Setup Time, EM_WAIT asserted before end of Strobe
14
tsu (EMOEL-EMWAIT)
4E+3
4E+3
4E+3
ns
Phase(2)
WRITES
Setup Time, EM_WAIT asserted before end of Strobe
28
tsu (EMWEL-EMWAIT)
4E+3
4E+3
4E+3
ns
Phase(2)
(1)
E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL0 output clock divided by 4.5. As an example, when
SYSCLK3 is selected and set to 100MHz, E=10ns
(2)
Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAIT must be asserted to add extended
wait states. Figure 6-14 and Figure 6-15 describe EMIF transactions that include extended wait states inserted during the STROBE
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where
the HOLD phase would begin if there were no extended wait cycles.
Table 6-22. Switching Characteristics for EMIFA Asynchronous Memory Interface (1) (2) (3)
1.3V, 1.2V, 1.1V, 1.0V
NO
PARAMETER
UNIT
.
MIN
Nom
MAX
READS and WRITES
1
td(TURNAROUND)
Turn around time
(TA)*E - 3
(TA)*E
(TA)*E + 3
ns
READS
(RS+RST+RH)*E
(RS+RST+RH)*E
EMIF read cycle time (EW = 0)
(RS+RST+RH)*E
ns
- 3
+ 3
3
tc(EMRCYCLE)
(RS+RST+RH+(E
(RS+RST+RH+(EW (RS+RST+RH+(E
EMIF read cycle time (EW = 1)
ns
WC*16))*E - 3
C*16))*E
WC*16))*E + 3
Output setup time, EMA_CE[5:2] low to
(RS)*E-3
(RS)*E
(RS)*E+3
ns
EMA_OE low (SS = 0)
4
tsu(EMCEL-EMOEL)
Output setup time, EMA_CE[5:2] low to
-3
0
+3
ns
EMA_OE low (SS = 1)
Output hold time, EMA_OE high to
(RH)*E - 3
(RH)*E
(RH)*E + 3
ns
EMA_CE[5:2] high (SS = 0)
5
th(EMOEH-EMCEH)
Output hold time, EMA_OE high to
-3
0
+3
ns
EMA_CE[5:2] high (SS = 1)
Output setup time, EMA_BA[1:0] valid to
6
tsu(EMBAV-EMOEL)
(RS)*E-3
(RS)*E
(RS)*E+3
ns
EMA_OE low
Output hold time, EMA_OE high to
7
th(EMOEH-EMBAIV)
(RH)*E-3
(RH)*E
(RH)*E+3
ns
EMA_BA[1:0] invalid
Output setup time, EMA_A[13:0] valid to
8
tsu(EMBAV-EMOEL)
(RS)*E-3
(RS)*E
(RS)*E+3
ns
EMA_OE low
Output hold time, EMA_OE high to
9
th(EMOEH-EMAIV)
(RH)*E-3
(RH)*E
(RH)*E+3
ns
EMA_A[13:0] invalid
(1)
TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold,
MEWC = Maximum external wait cycles. These parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle
Configuration Registers. These support the following range of values: TA[4-1], RS[16-1], RST[64-1], RH[8-1], WS[16-1], WST[64-1],
WH[8-1], and MEW[1-256].
(2)
E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL0 output clock divided by 4.5. As an example, when
SYSCLK3 is selected and set to 100MHz, E=10ns.
(3)
EWC = external wait cycles determined by EMA_WAIT input signal. EWC supports the following range of values EWC[256-1]. Note that
the maximum wait time before timeout is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register.
Copyright © 2010, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
97
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