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74HC590 Fiches technique(PDF) 10 Page - NXP Semiconductors |
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74HC590 Fiches technique(HTML) 10 Page - NXP Semiconductors |
10 / 21 page 74HC590_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 28 April 2009 10 of 21 NXP Semiconductors 74HC590 8-bit binary counter with output register; 3-state [1] tpd is the same as tPHL, tPLH. [2] ten is the same as tPZH and tPZL. [3] tdis is the same as tPLZ and tPHZ. [4] CPD is used to determine the dynamic power dissipation (PD in µW). PD =CPD × VCC2 × fi × N+ ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(C L × VCC 2 × f o) = sum of outputs. th hold time CE to CPC; see Figure 13 VCC = 2.0 V 0 - - 0 - 0 - ns VCC = 4.5 V 0 - - 0 - 0 - ns VCC = 6.0 V 0 - - 0 - 0 - ns trec recovery time MRC to CPC; see Figure 11 VCC = 2.0 V 75 28 - 95 - 110 - ns VCC = 4.5 V 15 7 - 19 - 22 - ns VCC = 6.0 V 13 6 - 16 - 19 - ns fmax maximum frequency CPC or CPR; see Figure 9 and Figure 10 VCC = 2.0 V 6.6 16 - 5.2 - 4.4 - MHz VCC = 4.5 V 33 52 - 26 - 22 - MHz VCC = 6.0 V 39 61 - 31 - 26 - MHz CPD power dissipation capacitance VI = GND to VCC [4] -44- - - - - pF Table 7. Dynamic characteristics …continued GND (ground = 0 V); for test circuit see Figure 15. Symbol Parameter Conditions 25 °C −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max |
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