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AM1707BZKBD3 Fiches technique(PDF) 44 Page - Texas Instruments |
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AM1707BZKBD3 Fiches technique(HTML) 44 Page - Texas Instruments |
44 / 155 page PLLDIV1 (/1) SYSCLK1 PLLDIV2 (/2) SYSCLK2 PLLDIV3 (/3) SYSCLK3 PLLDIV4 (/4) SYSCLK4 PLLDIV5 (/3) SYSCLK5 PLLDIV7 (/6) SYSCLK7 DIV4.5 1 0 EMIFA Internal Clock Source CFGCHIP3[EMA_CLKSRC] DIV4.5 EMIFB Internal Clock Source CFGCHIP3[EMB_CLKSRC] 1 0 Pre-Div PLLM PLLEN AUXCLK 0 1 PLL Post-Div CLKMODE 1 0 Square Wave Crystal OSCIN 2000 N Max PLL Lock Time = m where N = Pre-Divider Ratio M = PLL Multiplier AM1705 SPRS657A – FEBRUARY 2010 – REVISED APRIL 2010 www.ti.com Figure 6-9. PLL Topology Table 6-5. Allowed PLL Operating Conditions Default No. PARAMETER MIN MAX UNIT Value PLLRST: Assertion time during 1 N/A 1000 N/A ns initialization Lock time: The time that the application has to wait for the PLL to acquire locks OSCIN 2 N/A N/A before setting PLLEN, after changing cycles PREDIV, PLLM, or OSCIN (1) 3 PREDIV /1 /1 /32 ns PLL input frequency 4 12 50 MHz ( PLLREF) 5 PLL multiplier values (PLLM) (1) x20 x4 x32 6 PLL output frequency. ( PLLOUT ) N/A 400 600(2) MHz 7 POSTDIV /1 /2(2) /32 ns (1) The multiplier values must be chosen such that the PLL output frequency (at PLLOUT) is between 400 and 600 MHz, but the frequency going into the SYSCLK dividers (after the post divider) cannot exceed 300 MHz. The Post Divider and SYSCLK divider values must be chosen such that the CPU clocks do not exceed 300 MHz. (2) PLL post divider / 2 must be used. The /4.5 clock path can be used to generate an EMIF clock from the undivided (i.e. 600 MHz) PLL output clock. 44 Peripheral Information and Electrical Specifications Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1705 |
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