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74HC21D Fiches technique(PDF) 3 Page - NXP Semiconductors |
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74HC21D Fiches technique(HTML) 3 Page - NXP Semiconductors |
3 / 14 page 74HC21_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 7 May 2009 3 of 14 NXP Semiconductors 74HC21 Dual 4-input AND gate 5.2 Pin description 6. Functional description [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. 7. Limiting values [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For DIP14 package: Ptot derates linearly with 12 mW/K above 70 °C. For SO14 package: Ptot derates linearly with 8 mW/K above 70 °C. For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 °C. Table 2. Pin description Symbol Pin Description 1A, 1B, 1C, 1D 1, 2, 4, 5 data input n.c. 3, 11 not connected 1Y 6 data output GND 7 ground (0 V) 2Y 8 data output 2A, 2B, 2C, 2D 9, 10, 12, 13 data input VCC 14 supply voltage Table 3. Function table[1] Input Output nA nB nC nD nY L XXXL XL XXL XXL XL XXXL L HHHHH Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage −0.5 +7 V IIK input clamping current VI < −0.5 V or VI >VCC + 0.5 V [1] - ±20 mA IOK output clamping current VO < −0.5 V or VO >VCC + 0.5 V [1] - ±20 mA IO output current −0.5 V < VO < VCC + 0.5 V - ±25 mA ICC supply current - 50 mA IGND ground current −50 - mA Tstg storage temperature −65 +150 °C Ptot total power dissipation [2] DIP14 package - 750 mW SO14 and (T)SSOP14 packages - 500 mW |
Numéro de pièce similaire - 74HC21D |
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Description similaire - 74HC21D |
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