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AM1808_1004 Fiches technique(PDF) 100 Page - Texas Instruments |
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AM1808_1004 Fiches technique(HTML) 100 Page - Texas Instruments |
100 / 264 page AM1808 SPRS653A – FEBRUARY 2010 – REVISED APRIL 2010 www.ti.com 6.10.5 EMIFA Electrical Data/Timing Table 6-19 through Table 6-22 assume testing over recommended operating conditions. Table 6-19. Timing Requirements for EMIFA SDRAM Interface 1.3V, 1.2V 1.1V 1.0V NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX Input setup time, read data valid on EMA_D[15:0] before 19 tsu(EMA_DV-EM_CLKH) 2 3 3 ns EMA_CLK rising Input hold time, read data valid on EMA_D[15:0] after 20 th(CLKH-DIV) 1.6 1.6 1.6 ns EMA_CLK rising Table 6-20. Switching Characteristics for EMIFA SDRAM Interface 1.3V, 1.2V 1.1V 1.0V NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX 1 tc(CLK) Cycle time, EMIF clock EMA_CLK 10 15 20 ns 2 tw(CLK) Pulse width, EMIF clock EMA_CLK high or low 3 5 8 ns 3 td(CLKH-CSV) Delay time, EMA_CLK rising to EMA_CS[0] valid 7 9.5 13 ns 4 toh(CLKH-CSIV) Output hold time, EMA_CLK rising to EMA_CS[0] invalid 1 1 1 ns 5 td(CLKH-DQMV) Delay time, EMA_CLK rising to EMA_WE_DQM[1:0] valid 7 9.5 13 ns Output hold time, EMA_CLK rising to EMA_WE_DQM[1:0] 6 toh(CLKH-DQMIV) 1 1 1 ns invalid Delay time, EMA_CLK rising to EMA_A[12:0] and 7 td(CLKH-AV) 7 9.5 13 ns EMA_BA[1:0] valid Output hold time, EMA_CLK rising to EMA_A[12:0] and 8 toh(CLKH-AIV) 1 1 1 ns EMA_BA[1:0] invalid 9 td(CLKH-DV) Delay time, EMA_CLK rising to EMA_D[15:0] valid 7 9.5 13 ns 10 toh(CLKH-DIV) Output hold time, EMA_CLK rising to EMA_D[15:0] invalid 1 1 1 ns 11 td(CLKH-RASV) Delay time, EMA_CLK rising to EMA_RAS valid 7 9.5 13 ns 12 toh(CLKH-RASIV) Output hold time, EMA_CLK rising to EMA_RAS invalid 1 1 1 ns 13 td(CLKH-CASV) Delay time, EMA_CLK rising to EMA_CAS valid 7 9.5 13 ns 14 toh(CLKH-CASIV) Output hold time, EMA_CLK rising to EMA_CAS invalid 1 1 1 ns 15 td(CLKH-WEV) Delay time, EMA_CLK rising to EMA_WE valid 7 9.5 13 ns 16 toh(CLKH-WEIV) Output hold time, EMA_CLK rising to EMA_WE invalid 1 1 1 ns 17 tdis(CLKH-DHZ) Delay time, EMA_CLK rising to EMA_D[15:0] tri-stated 7 9.5 13 ns 18 tena(CLKH-DLZ) Output hold time, EMA_CLK rising to EMA_D[15:0] driving 1 1 1 ns 100 Peripheral Information and Electrical Specifications Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 |
Numéro de pièce similaire - AM1808_1004 |
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Description similaire - AM1808_1004 |
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