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74HCT165D Fiches technique(PDF) 11 Page - NXP Semiconductors |
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74HCT165D Fiches technique(HTML) 11 Page - NXP Semiconductors |
11 / 22 page 74HC_HCT165_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 14 March 2008 11 of 22 NXP Semiconductors 74HC165; 74HCT165 8-bit parallel-in/serial out shift register [1] tpd is the same as tPHL and tPLH. [2] tt is the same as tTHL and tTLH. [3] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + Σ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; Σ (CL × VCC2 × fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in V. 12. Waveforms CPD power dissipation capacitance per package; VI = GND to VCC − 1.5 V [3] -35- - - - - pF Table 7. Dynamic characteristics …continued GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 12 Symbol Parameter Conditions 25 °C −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. The clock (CP) or clock enable (CE) to output (Q7 or Q7) propagation delays, the clock pulse width, the maximum clock frequency and the output transition times mna987 CP or CE input Q7 or Q7 output tPHL tTHL tTLH tPLH tW 1/fmax VM VOH VI GND VOL VM |
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