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74AUP1G0832GW Fiches technique(PDF) 2 Page - NXP Semiconductors |
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74AUP1G0832GW Fiches technique(HTML) 2 Page - NXP Semiconductors |
2 / 16 page 74AUP1G0832_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 3 July 2009 2 of 16 NXP Semiconductors 74AUP1G0832 Low-power 3-input AND-OR gate 3. Ordering information 4. Marking [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP1G0832GW −40 °C to +125 °C SC-88 plastic surface-mounted package; 6 leads SOT363 74AUP1G0832GM −40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1 × 1.45 × 0.5 mm SOT886 74AUP1G0832GF −40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1 × 1 × 0.5 mm SOT891 Table 2. Marking Type number Marking code[1] 74AUP1G0832GW aY 74AUP1G0832GM aY 74AUP1G0832GF aY Fig 1. Logic symbol 001aad943 1 3 6 A B C 4 Y |
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