Moteur de recherche de fiches techniques de composants électroniques
  French  ▼
ALLDATASHEET.FR

X  

74AUP1G74DC Fiches technique(PDF) 1 Page - NXP Semiconductors

No de pièce 74AUP1G74DC
Description  Low-power D-type flip-flop with set and reset; positive-edge trigger
Download  24 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricant  NXP [NXP Semiconductors]
Site Internet  http://www.nxp.com
Logo NXP - NXP Semiconductors

74AUP1G74DC Fiches technique(HTML) 1 Page - NXP Semiconductors

  74AUP1G74DC Datasheet HTML 1Page - NXP Semiconductors 74AUP1G74DC Datasheet HTML 2Page - NXP Semiconductors 74AUP1G74DC Datasheet HTML 3Page - NXP Semiconductors 74AUP1G74DC Datasheet HTML 4Page - NXP Semiconductors 74AUP1G74DC Datasheet HTML 5Page - NXP Semiconductors 74AUP1G74DC Datasheet HTML 6Page - NXP Semiconductors 74AUP1G74DC Datasheet HTML 7Page - NXP Semiconductors 74AUP1G74DC Datasheet HTML 8Page - NXP Semiconductors 74AUP1G74DC Datasheet HTML 9Page - NXP Semiconductors Next Button
Zoom Inzoom in Zoom Outzoom out
 1 / 24 page
background image
1.
General description
The 74AUP1G74 provides a low-power, low-voltage single positive-edge triggered D-type
flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and
complementary Q and Q outputs. The SD and RD are asynchronous active LOW inputs
and operate independently of the clock input. Information on the data input is transferred
to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be
stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
2.
Features
I Wide supply voltage range from 0.8 V to 3.6 V
I High noise immunity
I Complies with JEDEC standards:
N JESD8-12 (0.8 V to 1.3 V)
N JESD8-11 (0.9 V to 1.65 V)
N JESD8-7 (1.2 V to 1.95 V)
N JESD8-5 (1.8 V to 2.7 V)
N JESD8-B (2.7 V to 3.6 V)
I ESD protection:
N HBM JESD22-A114E Class 3A exceeds 5000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101C exceeds 1000 V
I Low static power consumption; ICC = 0.9 µA (maximum)
I Latch-up performance exceeds 100 mA per JESD 78 Class II
I Inputs accept voltages up to 3.6 V
I Low noise overshoot and undershoot < 10 % of VCC
I IOFF circuitry provides partial Power-down mode operation
I Multiple package options
I Specified from −40 °Cto+85 °C and −40 °C to +125 °C
74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge
trigger
Rev. 04 — 3 June 2008
Product data sheet


Numéro de pièce similaire - 74AUP1G74DC

FabricantNo de pièceFiches techniqueDescription
logo
NXP Semiconductors
74AUP1G74DC PHILIPS-74AUP1G74DC Datasheet
112Kb / 23P
   Low-power D-type flip-flop with set and reset; positive-edge trigger
Rev. 01-25 August 2006
logo
Nexperia B.V. All right...
74AUP1G74DC NEXPERIA-74AUP1G74DC Datasheet
349Kb / 26P
   Low-power D-type flip-flop with set and reset; positive-edge trigger
Rev. 13 - 23 January 2023
74AUP1G74DC-Q100 NEXPERIA-74AUP1G74DC-Q100 Datasheet
243Kb / 20P
   Low-power D-type flip-flop with set and reset; positive-edge trigger
More results

Description similaire - 74AUP1G74DC

FabricantNo de pièceFiches techniqueDescription
logo
Nexperia B.V. All right...
74AUP1G74-Q100 NEXPERIA-74AUP1G74-Q100 Datasheet
243Kb / 20P
   Low-power D-type flip-flop with set and reset; positive-edge trigger
74AUP1G74 NEXPERIA-74AUP1G74 Datasheet
349Kb / 26P
   Low-power D-type flip-flop with set and reset; positive-edge trigger
Rev. 13 - 23 January 2023
logo
NXP Semiconductors
74AUP1G74 PHILIPS-74AUP1G74 Datasheet
112Kb / 23P
   Low-power D-type flip-flop with set and reset; positive-edge trigger
Rev. 01-25 August 2006
74LVC74A PHILIPS-74LVC74A Datasheet
99Kb / 10P
   Dual D-type flip-flop with set and reset; positive-edge trigger
1998 Jun 17
74LVC1G74DC.125 NXP-74LVC1G74DC.125 Datasheet
299Kb / 25P
   Single D-type flip-flop with set and reset; positive edge trigger
Rev. 12-2 April 2013
logo
Integral Corp.
IN74LV74 INTEGRAL-IN74LV74 Datasheet
161Kb / 7P
   Dual D-type flip-flop with set and reset; positive-edge trigger
logo
Nexperia B.V. All right...
74HC74-Q100 NEXPERIA-74HC74-Q100 Datasheet
798Kb / 19P
   Dual D-type flip-flop with set and reset; positive edge-trigger
74LVC74A-Q100 NEXPERIA-74LVC74A-Q100 Datasheet
722Kb / 18P
   Dual D-type flip-flop with set and reset; positive-edge trigger
74LV74 NEXPERIA-74LV74 Datasheet
251Kb / 15P
   Dual D-type flip-flop with set and reset; positive-edge trigger
Rev. 5 - 24 March 2021
logo
NXP Semiconductors
74LVC1G74 NXP-74LVC1G74_10 Datasheet
202Kb / 25P
   Single D-type flip-flop with set and reset; positive edge trigger
Rev. 9-5 August 2010
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24


Fiches technique Télécharger

Go To PDF Page


Lien URL




Politique de confidentialité
ALLDATASHEET.FR
ALLDATASHEET vous a-t-il été utile ?  [ DONATE ] 

À propos de Alldatasheet   |   Publicité   |   Contactez-nous   |   Politique de confidentialité   |   Echange de liens   |   Fabricants
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com