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74ABT823 Fiches technique(PDF) 9 Page - NXP Semiconductors |
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74ABT823 Fiches technique(HTML) 9 Page - NXP Semiconductors |
9 / 17 page 74ABT823_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 23 March 2010 9 of 17 NXP Semiconductors 74ABT823 9-bit D-type flip-flop with reset and enable; 3-state VM = 1.5 V The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 7. Set-up and hold times data output (Dn) to clock (CP) and clock enable input (CE) to clock (CP) 001aac447 GND GND th(H) tsu(H) th(L) tsu(L) VM VM VI VI CP input Dn, CE input VM = 1.5 V VOL and VOH are typical voltage output levels that occur with the output load Fig 8. 3-state output (Qn) enable and disable times 001aac448 tPZL Qn output Qn output OE input VOL VOH VI VM GND 3.5 V GND tPLZ tPZH tPHZ VOL + 0.3 V VOH − 0.3 V VM VM |
Numéro de pièce similaire - 74ABT823 |
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Description similaire - 74ABT823 |
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