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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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DAC3283 Fiches technique(PDF) 3 Page - Texas Instruments |
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DAC3283 Fiches technique(HTML) 3 Page - Texas Instruments |
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3 / 50 page  1 2 3 4 5 6 7 8 9 10 11 12 35 34 33 32 31 30 29 28 27 26 25 DAC3283 RGZPackage 48-QFN 7x7mm (TopView ) 36 GND DACCLKN D1P D1N D0P D0N TXENABLE SDIO SCLK SDENB D6N D6P D7N D7P DIGVDD18 OSTRN OSTRP DACCLKP DACVDD18 CLKVDD18 DACVDD18 CLKVDD18 ALARM_SDO DIGVDD18 DAC3283 www.ti.com SLAS693A – MARCH 2010 – REVISED APRIL 2010 DAC3283 RGZ PACKAGE (TOP VIEW) TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NAME NO. 37, 40, 42, Analog supply voltage. (3.3 V) AVDD33 I 45, 48 1.8V CMOS output for ALARM condition. The ALARM output functionality is defined through the CONFIG6 register. Default polarity is active low, but can be changed to active high via CONFIG0 ALARM_SDO 34 O alarm_pol control bit. Optionally, it can be used as the uni-directional data output in 4-pin serial interface mode (CONFIG 23 sif4_ena = '1'). BIASJ 43 O Full-scale output current bias. For 20mA full-scale output current, connect a 960 Ω resistor to GND. Internal clock buffer supply voltage. (1.8 V) It is recommended to isolate this supply from DACVDD18 CLKVDD18 1, 35 I and DIGVDD18. LVDS positive input data bits 0 through 7. Each positive/negative LVDS pair has an internal 100 Ω termination resistor. Data format relative to DATACLKP/N clock is Double Data Rate (DDR) with two data transfers per DATACKP/N clock cycle. Dual channel 16-bit data is transferred byte-wide on this 9, 11, 13, single 8-bit data bus using FRAMEP/N as a frame strobe indicator. D[7..0]P 15, 21, 23, I D7P is most significant data bit (MSB) – pin 9 25, 27 D0P is least significant data bit (LSB) – pin 27 The order of the bus can be reversed via CONFIG19 rev bit. LVDS negative input data bits 0 through 15. (See D[7:0]P description above) 10, 12, 14, D[7..0]N 16, 22, 24, I D7N is most significant data bit (MSB) – pin 10 26, 28 D0N is least significant data bit (LSB) – pin 28 DACCLKP 3 I Positive external LVPECL clock input for DAC core with a self-bias of approximately CLKVDD18/2. DACCLKN 4 I Complementary external LVPECL clock input for DAC core. (see the DACCLKP description) DAC core supply voltage. (1.8 V) It is recommended to isolate this supply from CLKVDD18 and DACVDD18 2, 36 I DIGVDD18. Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Link(s): DAC3283 |
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