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AD6659BCPZ-80 Fiches technique(PDF) 10 Page - Analog Devices |
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AD6659BCPZ-80 Fiches technique(HTML) 10 Page - Analog Devices |
10 / 40 page AD6659 Rev. | Page 10 of 40 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK+ CLK– SYNC NC NC NC NC (LSB) D0B D1B DRVDD D2B D3B D4B D5B D6B D7B PDWN OEB CSB SCLK/DFS SDIO/DCS ORA D11A (MSB) D10A D9A D8A D7A DRVDD D6A D5A D4A D3A 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB GROUND TO ENSURE PROPER HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS. AD6659 TOP VIEW (Not to Scale) Figure 5. Pin Configuration Table 8. Pin Function Descriptions Pin No. Mnemonic Description 0, EP AGND Exposed paddle is the only ground connection for the chip. It must be connected to the printed circuit board (PCB) AGND. 1, 2 CLK+, CLK− Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs. 3 SYNC Digital Input. SYNC input to clock divider. 30 kΩ internal pull-down. 4 to 7, 25 to 27, 29 NC Do Not Connect. 8, 9, 11 to 18, 20, 21 D0B to D11B Channel B Digital Outputs. D11B is the MSB and D0B is the LSB. 10, 19, 28, 37 DRVDD Digital Output Driver Supply (1.8 V to 3.3 V). 22 ORB Channel B Out-of-Range Digital Output. 23 DCOB Channel B Data Clock Digital Output. 24 DCOA Channel A Data Clock Digital Output. 30 to 36, 38 to 42 D0A to D11A Channel A Digital Outputs. D11A is the MSB and D0A is the LSB. 43 ORA Channel A Out-of-Range Digital Output. 44 SDIO/DCS SPI Data Input/Output (SDIO). The SDIO function provides bidirectional SPI data I/O in SPI mode with a 30 kΩ internal pull-down in SPI mode. The duty cycle stabilizer (DCS pin function) is the static enable input for the duty cycle stabilizer in non-SPI mode with a 30 kΩ internal pull-up in non-SPI (DCS) mode. 45 SCLK/DFS SPI Clock (SCLK) Input in SPI Mode/Data Format Select (DFS). 30 kΩ internal pull-down for both SCLK and DFS. The DFS function provides static control of data output format in non-SPI mode. When DFS is high, it equals twos complement output. When DFS is low, it equals offset binary output. 46 CSB SPI Chip Select. Active low enable; 30 kΩ internal pull-up. 47 OEB Digital Input. When OEB is low, it enables the Channel A and Channel B digital outputs; when OEB is high, the outputs are tristated. 30 kΩ internal pull-down. 48 PDWN Digital Input. 30 kΩ internal pull-down. When PDWN is high, it powers down the device. When PDWN is low, the device runs in normal operation. |
Numéro de pièce similaire - AD6659BCPZ-80 |
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Description similaire - AD6659BCPZ-80 |
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